* IN THE SOFTWARE.
*/
-extern "C" {
#include "main/macros.h"
-#include "program/register_allocate.h"
-} /* extern "C" */
-
+#include "util/register_allocate.h"
#include "brw_vec4.h"
#include "brw_vs.h"
+#include "brw_cfg.h"
using namespace brw;
assign(unsigned int *reg_hw_locations, backend_reg *reg)
{
if (reg->file == GRF) {
- reg->reg = reg_hw_locations[reg->reg];
+ assert(reg->reg_offset >= 0);
+ reg->reg = reg_hw_locations[reg->reg] + reg->reg_offset;
+ reg->reg_offset = 0;
}
}
bool
vec4_visitor::reg_allocate_trivial()
{
- unsigned int hw_reg_mapping[this->virtual_grf_count];
- bool virtual_grf_used[this->virtual_grf_count];
- int i;
+ unsigned int hw_reg_mapping[this->alloc.count];
+ bool virtual_grf_used[this->alloc.count];
int next;
/* Calculate which virtual GRFs are actually in use after whatever
* optimization passes have occurred.
*/
- for (int i = 0; i < this->virtual_grf_count; i++) {
+ for (unsigned i = 0; i < this->alloc.count; i++) {
virtual_grf_used[i] = false;
}
- foreach_in_list(vec4_instruction, inst, &instructions) {
+ foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
if (inst->dst.file == GRF)
virtual_grf_used[inst->dst.reg] = true;
- for (int i = 0; i < 3; i++) {
+ for (unsigned i = 0; i < 3; i++) {
if (inst->src[i].file == GRF)
virtual_grf_used[inst->src[i].reg] = true;
}
}
hw_reg_mapping[0] = this->first_non_payload_grf;
- next = hw_reg_mapping[0] + this->virtual_grf_sizes[0];
- for (i = 1; i < this->virtual_grf_count; i++) {
+ next = hw_reg_mapping[0] + this->alloc.sizes[0];
+ for (unsigned i = 1; i < this->alloc.count; i++) {
if (virtual_grf_used[i]) {
hw_reg_mapping[i] = next;
- next += this->virtual_grf_sizes[i];
+ next += this->alloc.sizes[i];
}
}
prog_data->total_grf = next;
- foreach_in_list(vec4_instruction, inst, &instructions) {
+ foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
assign(hw_reg_mapping, &inst->dst);
assign(hw_reg_mapping, &inst->src[0]);
assign(hw_reg_mapping, &inst->src[1]);
* SEND-from-GRF sources cannot be split, so we also need classes for each
* potential message length.
*/
- const int class_count = 2;
- const int class_sizes[class_count] = {1, 2};
+ const int class_count = MAX_VGRF_SIZE;
+ int class_sizes[MAX_VGRF_SIZE];
+
+ for (int i = 0; i < class_count; i++)
+ class_sizes[i] = i + 1;
/* Compute the total number of registers across all classes. */
int ra_reg_count = 0;
* between them and the base GRF registers (and also each other).
*/
int reg = 0;
+ unsigned *q_values[MAX_VGRF_SIZE];
for (int i = 0; i < class_count; i++) {
int class_reg_count = base_reg_count - (class_sizes[i] - 1);
screen->vec4_reg_set.classes[i] = ra_alloc_reg_class(screen->vec4_reg_set.regs);
+ q_values[i] = new unsigned[MAX_VGRF_SIZE];
+
for (int j = 0; j < class_reg_count; j++) {
ra_class_add_reg(screen->vec4_reg_set.regs, screen->vec4_reg_set.classes[i], reg);
reg++;
}
+
+ for (int j = 0; j < class_count; j++) {
+ /* Calculate the q values manually because the algorithm used by
+ * ra_set_finalize() to do it has higher complexity affecting the
+ * start-up time of some applications. q(i, j) is just the maximum
+ * number of registers from class i a register from class j can
+ * conflict with.
+ */
+ q_values[i][j] = class_sizes[i] + class_sizes[j] - 1;
+ }
}
assert(reg == ra_reg_count);
- ra_set_finalize(screen->vec4_reg_set.regs, NULL);
+ ra_set_finalize(screen->vec4_reg_set.regs, q_values);
+
+ for (int i = 0; i < MAX_VGRF_SIZE; i++)
+ delete[] q_values[i];
}
void
vec4_visitor::reg_allocate()
{
struct intel_screen *screen = brw->intelScreen;
- unsigned int hw_reg_mapping[virtual_grf_count];
+ unsigned int hw_reg_mapping[alloc.count];
int payload_reg_count = this->first_non_payload_grf;
/* Using the trivial allocator can be useful in debugging undefined
calculate_live_intervals();
- int node_count = virtual_grf_count;
+ int node_count = alloc.count;
int first_payload_node = node_count;
node_count += payload_reg_count;
struct ra_graph *g =
ra_alloc_interference_graph(screen->vec4_reg_set.regs, node_count);
- for (int i = 0; i < virtual_grf_count; i++) {
- int size = this->virtual_grf_sizes[i];
- assert(size >= 1 && size <= 2 &&
- "Register allocation relies on split_virtual_grfs().");
+ for (unsigned i = 0; i < alloc.count; i++) {
+ int size = this->alloc.sizes[i];
+ assert(size >= 1 && size <= MAX_VGRF_SIZE);
ra_set_node_class(g, i, screen->vec4_reg_set.classes[size - 1]);
- for (int j = 0; j < i; j++) {
+ for (unsigned j = 0; j < i; j++) {
if (virtual_grf_interferes(i, j)) {
ra_add_node_interference(g, i, j);
}
setup_payload_interference(g, first_payload_node, node_count);
- if (!ra_allocate_no_spills(g)) {
+ if (!ra_allocate(g)) {
/* Failed to allocate registers. Spill a reg, and the caller will
* loop back into here to try again.
*/
* numbers.
*/
prog_data->total_grf = payload_reg_count;
- for (int i = 0; i < virtual_grf_count; i++) {
+ for (unsigned i = 0; i < alloc.count; i++) {
int reg = ra_get_node_reg(g, i);
hw_reg_mapping[i] = screen->vec4_reg_set.ra_reg_to_grf[reg];
prog_data->total_grf = MAX2(prog_data->total_grf,
- hw_reg_mapping[i] + virtual_grf_sizes[i]);
+ hw_reg_mapping[i] + alloc.sizes[i]);
}
- foreach_in_list(vec4_instruction, inst, &instructions) {
+ foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
assign(hw_reg_mapping, &inst->dst);
assign(hw_reg_mapping, &inst->src[0]);
assign(hw_reg_mapping, &inst->src[1]);
{
float loop_scale = 1.0;
- for (int i = 0; i < this->virtual_grf_count; i++) {
+ for (unsigned i = 0; i < this->alloc.count; i++) {
spill_costs[i] = 0.0;
- no_spill[i] = virtual_grf_sizes[i] != 1;
+ no_spill[i] = alloc.sizes[i] != 1;
}
/* Calculate costs for spilling nodes. Call it a cost of 1 per
* spill/unspill we'll have to do, and guess that the insides of
* loops run 10 times.
*/
- foreach_in_list(vec4_instruction, inst, &instructions) {
+ foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
for (unsigned int i = 0; i < 3; i++) {
if (inst->src[i].file == GRF) {
spill_costs[inst->src[i].reg] += loop_scale;
int
vec4_visitor::choose_spill_reg(struct ra_graph *g)
{
- float spill_costs[this->virtual_grf_count];
- bool no_spill[this->virtual_grf_count];
+ float spill_costs[this->alloc.count];
+ bool no_spill[this->alloc.count];
evaluate_spill_costs(spill_costs, no_spill);
- for (int i = 0; i < this->virtual_grf_count; i++) {
+ for (unsigned i = 0; i < this->alloc.count; i++) {
if (!no_spill[i])
ra_set_node_spill_cost(g, i, spill_costs[i]);
}
void
vec4_visitor::spill_reg(int spill_reg_nr)
{
- assert(virtual_grf_sizes[spill_reg_nr] == 1);
+ assert(alloc.sizes[spill_reg_nr] == 1);
unsigned int spill_offset = c->last_scratch++;
/* Generate spill/unspill instructions for the objects being spilled. */
- foreach_in_list(vec4_instruction, inst, &instructions) {
+ foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
for (unsigned int i = 0; i < 3; i++) {
if (inst->src[i].file == GRF && inst->src[i].reg == spill_reg_nr) {
src_reg spill_reg = inst->src[i];
- inst->src[i].reg = virtual_grf_alloc(1);
+ inst->src[i].reg = alloc.allocate(1);
dst_reg temp = dst_reg(inst->src[i]);
- /* Only read the necessary channels, to avoid overwriting the rest
- * with data that may not have been written to scratch.
- */
- temp.writemask = 0;
- for (int c = 0; c < 4; c++)
- temp.writemask |= (1 << BRW_GET_SWZ(inst->src[i].swizzle, c));
- assert(temp.writemask != 0);
-
- emit_scratch_read(inst, temp, spill_reg, spill_offset);
+ emit_scratch_read(block, inst, temp, spill_reg, spill_offset);
}
}
if (inst->dst.file == GRF && inst->dst.reg == spill_reg_nr) {
- emit_scratch_write(inst, spill_offset);
+ emit_scratch_write(block, inst, spill_offset);
}
}
projects / mesa.git / blobdiff