i965: Refactor SIMD16-to-2xSIMD8 checks.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_reg_allocate.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index b944d454df6d7e537fbfe85950f371dedc13effa..31868240a0a29427ab7d2d5ff0e24cc65c05f4da 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -21,11 +21,8 @@
  * IN THE SOFTWARE.
  */
 
-extern "C" {
 #include "main/macros.h"
 #include "util/register_allocate.h"
-} /* extern "C" */
-
 #include "brw_vec4.h"
 #include "brw_vs.h"
 #include "brw_cfg.h"
@@ -38,7 +35,9 @@ static void
 assign(unsigned int *reg_hw_locations, backend_reg *reg)
 {
    if (reg->file == GRF) {
-      reg->reg = reg_hw_locations[reg->reg];
+      assert(reg->reg_offset >= 0);
+      reg->reg = reg_hw_locations[reg->reg] + reg->reg_offset;
+      reg->reg_offset = 0;
    }
 }
 
@@ -102,8 +101,11 @@ brw_vec4_alloc_reg_set(struct intel_screen *screen)
     * SEND-from-GRF sources cannot be split, so we also need classes for each
     * potential message length.
     */
-   const int class_count = 2;
-   const int class_sizes[class_count] = {1, 2};
+   const int class_count = MAX_VGRF_SIZE;
+   int class_sizes[MAX_VGRF_SIZE];
+
+   for (int i = 0; i < class_count; i++)
+      class_sizes[i] = i + 1;
 
    /* Compute the total number of registers across all classes. */
    int ra_reg_count = 0;
@@ -124,10 +126,13 @@ brw_vec4_alloc_reg_set(struct intel_screen *screen)
     * between them and the base GRF registers (and also each other).
     */
    int reg = 0;
+   unsigned *q_values[MAX_VGRF_SIZE];
    for (int i = 0; i < class_count; i++) {
       int class_reg_count = base_reg_count - (class_sizes[i] - 1);
       screen->vec4_reg_set.classes[i] = ra_alloc_reg_class(screen->vec4_reg_set.regs);
 
+      q_values[i] = new unsigned[MAX_VGRF_SIZE];
+
       for (int j = 0; j < class_reg_count; j++) {
         ra_class_add_reg(screen->vec4_reg_set.regs, screen->vec4_reg_set.classes[i], reg);
 
@@ -141,10 +146,23 @@ brw_vec4_alloc_reg_set(struct intel_screen *screen)
 
         reg++;
       }
+
+      for (int j = 0; j < class_count; j++) {
+         /* Calculate the q values manually because the algorithm used by
+          * ra_set_finalize() to do it has higher complexity affecting the
+          * start-up time of some applications.  q(i, j) is just the maximum
+          * number of registers from class i a register from class j can
+          * conflict with.
+          */
+         q_values[i][j] = class_sizes[i] + class_sizes[j] - 1;
+      }
    }
    assert(reg == ra_reg_count);
 
-   ra_set_finalize(screen->vec4_reg_set.regs, NULL);
+   ra_set_finalize(screen->vec4_reg_set.regs, q_values);
+
+   for (int i = 0; i < MAX_VGRF_SIZE; i++)
+      delete[] q_values[i];
 }
 
 void
@@ -194,8 +212,7 @@ vec4_visitor::reg_allocate()
 
    for (unsigned i = 0; i < alloc.count; i++) {
       int size = this->alloc.sizes[i];
-      assert(size >= 1 && size <= 2 &&
-             "Register allocation relies on split_virtual_grfs().");
+      assert(size >= 1 && size <= MAX_VGRF_SIZE);
       ra_set_node_class(g, i, screen->vec4_reg_set.classes[size - 1]);
 
       for (unsigned j = 0; j < i; j++) {