i965/vec4: Make with_writemask() non-static.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_reg_allocate.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index ab75a170e3332fdc76a494ecd3056001314714fe..3777027d0e49015662f5c223f89e2bb32ab560e7 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -96,9 +96,11 @@ vec4_visitor::reg_allocate_trivial()
    return true;
 }
 
-static void
-brw_alloc_reg_set(struct brw_context *brw, int base_reg_count)
+extern "C" void
+brw_vec4_alloc_reg_set(struct brw_context *brw)
 {
+   int base_reg_count = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
+
    /* After running split_virtual_grfs(), almost all VGRFs will be of size 1.
     * SEND-from-GRF sources cannot be split, so we also need classes for each
     * potential message length.
@@ -112,14 +114,14 @@ brw_alloc_reg_set(struct brw_context *brw, int base_reg_count)
       ra_reg_count += base_reg_count - (class_sizes[i] - 1);
    }
 
-   ralloc_free(brw->vs.ra_reg_to_grf);
-   brw->vs.ra_reg_to_grf = ralloc_array(brw, uint8_t, ra_reg_count);
-   ralloc_free(brw->vs.regs);
-   brw->vs.regs = ra_alloc_reg_set(brw, ra_reg_count);
+   ralloc_free(brw->vec4.ra_reg_to_grf);
+   brw->vec4.ra_reg_to_grf = ralloc_array(brw, uint8_t, ra_reg_count);
+   ralloc_free(brw->vec4.regs);
+   brw->vec4.regs = ra_alloc_reg_set(brw, ra_reg_count);
    if (brw->gen >= 6)
-      ra_set_allocate_round_robin(brw->vs.regs);
-   ralloc_free(brw->vs.classes);
-   brw->vs.classes = ralloc_array(brw, int, class_count + 1);
+      ra_set_allocate_round_robin(brw->vec4.regs);
+   ralloc_free(brw->vec4.classes);
+   brw->vec4.classes = ralloc_array(brw, int, class_count + 1);
 
    /* Now, add the registers to their classes, and add the conflicts
     * between them and the base GRF registers (and also each other).
@@ -127,17 +129,17 @@ brw_alloc_reg_set(struct brw_context *brw, int base_reg_count)
    int reg = 0;
    for (int i = 0; i < class_count; i++) {
       int class_reg_count = base_reg_count - (class_sizes[i] - 1);
-      brw->vs.classes[i] = ra_alloc_reg_class(brw->vs.regs);
+      brw->vec4.classes[i] = ra_alloc_reg_class(brw->vec4.regs);
 
       for (int j = 0; j < class_reg_count; j++) {
-        ra_class_add_reg(brw->vs.regs, brw->vs.classes[i], reg);
+        ra_class_add_reg(brw->vec4.regs, brw->vec4.classes[i], reg);
 
-        brw->vs.ra_reg_to_grf[reg] = j;
+        brw->vec4.ra_reg_to_grf[reg] = j;
 
         for (int base_reg = j;
              base_reg < j + class_sizes[i];
              base_reg++) {
-           ra_add_transitive_reg_conflict(brw->vs.regs, base_reg, reg);
+           ra_add_transitive_reg_conflict(brw->vec4.regs, base_reg, reg);
         }
 
         reg++;
@@ -145,15 +147,38 @@ brw_alloc_reg_set(struct brw_context *brw, int base_reg_count)
    }
    assert(reg == ra_reg_count);
 
-   ra_set_finalize(brw->vs.regs, NULL);
+   ra_set_finalize(brw->vec4.regs, NULL);
+}
+
+void
+vec4_visitor::setup_payload_interference(struct ra_graph *g,
+                                         int first_payload_node,
+                                         int reg_node_count)
+{
+   int payload_node_count = this->first_non_payload_grf;
+
+   for (int i = 0; i < payload_node_count; i++) {
+      /* Mark each payload reg node as being allocated to its physical register.
+       *
+       * The alternative would be to have per-physical register classes, which
+       * would just be silly.
+       */
+      ra_set_node_reg(g, first_payload_node + i, i);
+
+      /* For now, just mark each payload node as interfering with every other
+       * node to be allocated.
+       */
+      for (int j = 0; j < reg_node_count; j++) {
+         ra_add_node_interference(g, first_payload_node + i, j);
+      }
+   }
 }
 
 bool
 vec4_visitor::reg_allocate()
 {
    unsigned int hw_reg_mapping[virtual_grf_count];
-   int first_assigned_grf = this->first_non_payload_grf;
-   int base_reg_count = max_grf - first_assigned_grf;
+   int payload_reg_count = this->first_non_payload_grf;
 
    /* Using the trivial allocator can be useful in debugging undefined
     * register access as a result of broken optimization passes.
@@ -163,16 +188,17 @@ vec4_visitor::reg_allocate()
 
    calculate_live_intervals();
 
-   brw_alloc_reg_set(brw, base_reg_count);
-
-   struct ra_graph *g = ra_alloc_interference_graph(brw->vs.regs,
-                                                   virtual_grf_count);
+   int node_count = virtual_grf_count;
+   int first_payload_node = node_count;
+   node_count += payload_reg_count;
+   struct ra_graph *g =
+      ra_alloc_interference_graph(brw->vec4.regs, node_count);
 
    for (int i = 0; i < virtual_grf_count; i++) {
       int size = this->virtual_grf_sizes[i];
       assert(size >= 1 && size <= 2 &&
              "Register allocation relies on split_virtual_grfs().");
-      ra_set_node_class(g, i, brw->vs.classes[size - 1]);
+      ra_set_node_class(g, i, brw->vec4.classes[size - 1]);
 
       for (int j = 0; j < i; j++) {
         if (virtual_grf_interferes(i, j)) {
@@ -181,6 +207,8 @@ vec4_visitor::reg_allocate()
       }
    }
 
+   setup_payload_interference(g, first_payload_node, node_count);
+
    if (!ra_allocate_no_spills(g)) {
       /* Failed to allocate registers.  Spill a reg, and the caller will
        * loop back into here to try again.
@@ -199,11 +227,11 @@ vec4_visitor::reg_allocate()
     * regs in the register classes back down to real hardware reg
     * numbers.
     */
-   prog_data->total_grf = first_assigned_grf;
+   prog_data->total_grf = payload_reg_count;
    for (int i = 0; i < virtual_grf_count; i++) {
       int reg = ra_get_node_reg(g, i);
 
-      hw_reg_mapping[i] = first_assigned_grf + brw->vs.ra_reg_to_grf[reg];
+      hw_reg_mapping[i] = brw->vec4.ra_reg_to_grf[reg];
       prog_data->total_grf = MAX2(prog_data->total_grf,
                                  hw_reg_mapping[i] + virtual_grf_sizes[i]);
    }