i965: Fix handling of MESA_pack_invert in blit (PBO) readpixels.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_reg_allocate.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index fbd79d03a6a4a2d03c01518305d173066062c45a..95c8d9f705a1cea466b75ae96e869c444fc9bd47 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -96,8 +96,8 @@ vec4_visitor::reg_allocate_trivial()
    return true;
 }
 
-static void
-brw_alloc_reg_set(struct brw_context *brw)
+extern "C" void
+brw_vec4_alloc_reg_set(struct brw_context *brw)
 {
    int base_reg_count = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
 
@@ -114,14 +114,14 @@ brw_alloc_reg_set(struct brw_context *brw)
       ra_reg_count += base_reg_count - (class_sizes[i] - 1);
    }
 
-   ralloc_free(brw->vs.ra_reg_to_grf);
-   brw->vs.ra_reg_to_grf = ralloc_array(brw, uint8_t, ra_reg_count);
-   ralloc_free(brw->vs.regs);
-   brw->vs.regs = ra_alloc_reg_set(brw, ra_reg_count);
+   ralloc_free(brw->vec4.ra_reg_to_grf);
+   brw->vec4.ra_reg_to_grf = ralloc_array(brw, uint8_t, ra_reg_count);
+   ralloc_free(brw->vec4.regs);
+   brw->vec4.regs = ra_alloc_reg_set(brw, ra_reg_count);
    if (brw->gen >= 6)
-      ra_set_allocate_round_robin(brw->vs.regs);
-   ralloc_free(brw->vs.classes);
-   brw->vs.classes = ralloc_array(brw, int, class_count + 1);
+      ra_set_allocate_round_robin(brw->vec4.regs);
+   ralloc_free(brw->vec4.classes);
+   brw->vec4.classes = ralloc_array(brw, int, class_count + 1);
 
    /* Now, add the registers to their classes, and add the conflicts
     * between them and the base GRF registers (and also each other).
@@ -129,17 +129,17 @@ brw_alloc_reg_set(struct brw_context *brw)
    int reg = 0;
    for (int i = 0; i < class_count; i++) {
       int class_reg_count = base_reg_count - (class_sizes[i] - 1);
-      brw->vs.classes[i] = ra_alloc_reg_class(brw->vs.regs);
+      brw->vec4.classes[i] = ra_alloc_reg_class(brw->vec4.regs);
 
       for (int j = 0; j < class_reg_count; j++) {
-        ra_class_add_reg(brw->vs.regs, brw->vs.classes[i], reg);
+        ra_class_add_reg(brw->vec4.regs, brw->vec4.classes[i], reg);
 
-        brw->vs.ra_reg_to_grf[reg] = j;
+        brw->vec4.ra_reg_to_grf[reg] = j;
 
         for (int base_reg = j;
              base_reg < j + class_sizes[i];
              base_reg++) {
-           ra_add_transitive_reg_conflict(brw->vs.regs, base_reg, reg);
+           ra_add_transitive_reg_conflict(brw->vec4.regs, base_reg, reg);
         }
 
         reg++;
@@ -147,7 +147,7 @@ brw_alloc_reg_set(struct brw_context *brw)
    }
    assert(reg == ra_reg_count);
 
-   ra_set_finalize(brw->vs.regs, NULL);
+   ra_set_finalize(brw->vec4.regs, NULL);
 }
 
 void
@@ -188,18 +188,17 @@ vec4_visitor::reg_allocate()
 
    calculate_live_intervals();
 
-   brw_alloc_reg_set(brw);
-
    int node_count = virtual_grf_count;
    int first_payload_node = node_count;
    node_count += payload_reg_count;
-   struct ra_graph *g = ra_alloc_interference_graph(brw->vs.regs, node_count);
+   struct ra_graph *g =
+      ra_alloc_interference_graph(brw->vec4.regs, node_count);
 
    for (int i = 0; i < virtual_grf_count; i++) {
       int size = this->virtual_grf_sizes[i];
       assert(size >= 1 && size <= 2 &&
              "Register allocation relies on split_virtual_grfs().");
-      ra_set_node_class(g, i, brw->vs.classes[size - 1]);
+      ra_set_node_class(g, i, brw->vec4.classes[size - 1]);
 
       for (int j = 0; j < i; j++) {
         if (virtual_grf_interferes(i, j)) {
@@ -215,7 +214,10 @@ vec4_visitor::reg_allocate()
        * loop back into here to try again.
        */
       int reg = choose_spill_reg(g);
-      if (reg == -1) {
+      if (this->no_spills) {
+         fail("Failure to register allocate.  Reduce number of live "
+              "values to avoid this.");
+      } else if (reg == -1) {
          fail("no register to spill\n");
       } else {
          spill_reg(reg);
@@ -232,7 +234,7 @@ vec4_visitor::reg_allocate()
    for (int i = 0; i < virtual_grf_count; i++) {
       int reg = ra_get_node_reg(g, i);
 
-      hw_reg_mapping[i] = brw->vs.ra_reg_to_grf[reg];
+      hw_reg_mapping[i] = brw->vec4.ra_reg_to_grf[reg];
       prog_data->total_grf = MAX2(prog_data->total_grf,
                                  hw_reg_mapping[i] + virtual_grf_sizes[i]);
    }
@@ -292,8 +294,8 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill)
         loop_scale /= 10;
         break;
 
-      case VS_OPCODE_SCRATCH_READ:
-      case VS_OPCODE_SCRATCH_WRITE:
+      case SHADER_OPCODE_GEN4_SCRATCH_READ:
+      case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
          for (int i = 0; i < 3; i++) {
             if (inst->src[i].file == GRF)
                no_spill[inst->src[i].reg] = true;
@@ -357,7 +359,7 @@ vec4_visitor::spill_reg(int spill_reg_nr)
       }
    }
 
-   this->live_intervals_valid = false;
+   invalidate_live_intervals();
 }
 
 } /* namespace brw */