i965/fs: Lower 32x32 bit multiplication on BXT.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_reg_allocate.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index a286f8ace77fb73b08a6d0e402ccd1f77568ae3d..cd89edd64de7a4042ac4903457356cc9eb104b5e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -21,11 +21,8 @@
  * IN THE SOFTWARE.
  */
 
-extern "C" {
 #include "main/macros.h"
 #include "util/register_allocate.h"
-} /* extern "C" */
-
 #include "brw_vec4.h"
 #include "brw_vs.h"
 #include "brw_cfg.h"
@@ -38,7 +35,6 @@ static void
 assign(unsigned int *reg_hw_locations, backend_reg *reg)
 {
    if (reg->file == GRF) {
-      assert(reg->reg_offset >= 0);
       reg->reg = reg_hw_locations[reg->reg] + reg->reg_offset;
       reg->reg_offset = 0;
    }
@@ -95,10 +91,10 @@ vec4_visitor::reg_allocate_trivial()
 }
 
 extern "C" void
-brw_vec4_alloc_reg_set(struct intel_screen *screen)
+brw_vec4_alloc_reg_set(struct brw_compiler *compiler)
 {
    int base_reg_count =
-      screen->devinfo->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
+      compiler->devinfo->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
 
    /* After running split_virtual_grfs(), almost all VGRFs will be of size 1.
     * SEND-from-GRF sources cannot be split, so we also need classes for each
@@ -116,14 +112,14 @@ brw_vec4_alloc_reg_set(struct intel_screen *screen)
       ra_reg_count += base_reg_count - (class_sizes[i] - 1);
    }
 
-   ralloc_free(screen->vec4_reg_set.ra_reg_to_grf);
-   screen->vec4_reg_set.ra_reg_to_grf = ralloc_array(screen, uint8_t, ra_reg_count);
-   ralloc_free(screen->vec4_reg_set.regs);
-   screen->vec4_reg_set.regs = ra_alloc_reg_set(screen, ra_reg_count);
-   if (screen->devinfo->gen >= 6)
-      ra_set_allocate_round_robin(screen->vec4_reg_set.regs);
-   ralloc_free(screen->vec4_reg_set.classes);
-   screen->vec4_reg_set.classes = ralloc_array(screen, int, class_count);
+   ralloc_free(compiler->vec4_reg_set.ra_reg_to_grf);
+   compiler->vec4_reg_set.ra_reg_to_grf = ralloc_array(compiler, uint8_t, ra_reg_count);
+   ralloc_free(compiler->vec4_reg_set.regs);
+   compiler->vec4_reg_set.regs = ra_alloc_reg_set(compiler, ra_reg_count);
+   if (compiler->devinfo->gen >= 6)
+      ra_set_allocate_round_robin(compiler->vec4_reg_set.regs);
+   ralloc_free(compiler->vec4_reg_set.classes);
+   compiler->vec4_reg_set.classes = ralloc_array(compiler, int, class_count);
 
    /* Now, add the registers to their classes, and add the conflicts
     * between them and the base GRF registers (and also each other).
@@ -132,19 +128,19 @@ brw_vec4_alloc_reg_set(struct intel_screen *screen)
    unsigned *q_values[MAX_VGRF_SIZE];
    for (int i = 0; i < class_count; i++) {
       int class_reg_count = base_reg_count - (class_sizes[i] - 1);
-      screen->vec4_reg_set.classes[i] = ra_alloc_reg_class(screen->vec4_reg_set.regs);
+      compiler->vec4_reg_set.classes[i] = ra_alloc_reg_class(compiler->vec4_reg_set.regs);
 
       q_values[i] = new unsigned[MAX_VGRF_SIZE];
 
       for (int j = 0; j < class_reg_count; j++) {
-        ra_class_add_reg(screen->vec4_reg_set.regs, screen->vec4_reg_set.classes[i], reg);
+        ra_class_add_reg(compiler->vec4_reg_set.regs, compiler->vec4_reg_set.classes[i], reg);
 
-        screen->vec4_reg_set.ra_reg_to_grf[reg] = j;
+        compiler->vec4_reg_set.ra_reg_to_grf[reg] = j;
 
         for (int base_reg = j;
              base_reg < j + class_sizes[i];
              base_reg++) {
-           ra_add_transitive_reg_conflict(screen->vec4_reg_set.regs, base_reg, reg);
+           ra_add_transitive_reg_conflict(compiler->vec4_reg_set.regs, base_reg, reg);
         }
 
         reg++;
@@ -162,7 +158,7 @@ brw_vec4_alloc_reg_set(struct intel_screen *screen)
    }
    assert(reg == ra_reg_count);
 
-   ra_set_finalize(screen->vec4_reg_set.regs, q_values);
+   ra_set_finalize(compiler->vec4_reg_set.regs, q_values);
 
    for (int i = 0; i < MAX_VGRF_SIZE; i++)
       delete[] q_values[i];
@@ -195,7 +191,6 @@ vec4_visitor::setup_payload_interference(struct ra_graph *g,
 bool
 vec4_visitor::reg_allocate()
 {
-   struct intel_screen *screen = brw->intelScreen;
    unsigned int hw_reg_mapping[alloc.count];
    int payload_reg_count = this->first_non_payload_grf;
 
@@ -211,12 +206,12 @@ vec4_visitor::reg_allocate()
    int first_payload_node = node_count;
    node_count += payload_reg_count;
    struct ra_graph *g =
-      ra_alloc_interference_graph(screen->vec4_reg_set.regs, node_count);
+      ra_alloc_interference_graph(compiler->vec4_reg_set.regs, node_count);
 
    for (unsigned i = 0; i < alloc.count; i++) {
       int size = this->alloc.sizes[i];
       assert(size >= 1 && size <= MAX_VGRF_SIZE);
-      ra_set_node_class(g, i, screen->vec4_reg_set.classes[size - 1]);
+      ra_set_node_class(g, i, compiler->vec4_reg_set.classes[size - 1]);
 
       for (unsigned j = 0; j < i; j++) {
         if (virtual_grf_interferes(i, j)) {
@@ -252,7 +247,7 @@ vec4_visitor::reg_allocate()
    for (unsigned i = 0; i < alloc.count; i++) {
       int reg = ra_get_node_reg(g, i);
 
-      hw_reg_mapping[i] = screen->vec4_reg_set.ra_reg_to_grf[reg];
+      hw_reg_mapping[i] = compiler->vec4_reg_set.ra_reg_to_grf[reg];
       prog_data->total_grf = MAX2(prog_data->total_grf,
                                  hw_reg_mapping[i] + alloc.sizes[i]);
    }
@@ -344,7 +339,7 @@ void
 vec4_visitor::spill_reg(int spill_reg_nr)
 {
    assert(alloc.sizes[spill_reg_nr] == 1);
-   unsigned int spill_offset = c->last_scratch++;
+   unsigned int spill_offset = last_scratch++;
 
    /* Generate spill/unspill instructions for the objects being spilled. */
    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {