i965/vec4: Replace vec4_instruction::regs_written with ::size_written field in bytes.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_surface_builder.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp b/src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp
index a7c286d3ac1fc5e692f115ca0b96ecc4a4f3a634..19c685feea54d10fa683bbdb3d70cf4e6f8bbaa6 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp
@@ -71,7 +71,7 @@ namespace {
 
             bld.MOV(writemask(tmp, mask), src);
             if (n < 4)
-               bld.MOV(writemask(tmp, ~mask), 0);
+               bld.MOV(writemask(tmp, ~mask), brw_imm_d(0));
 
             return emit_stride(bld, src_reg(tmp), n, has_simd4x2 ? 1 : 4, 1);
          }
@@ -143,9 +143,9 @@ namespace brw {
             /* Emit the message send instruction. */
             const dst_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD, ret_sz);
             vec4_instruction *inst =
-               bld.emit(op, dst, src_reg(payload), usurface, arg);
+               bld.emit(op, dst, src_reg(payload), usurface, brw_imm_ud(arg));
             inst->mlen = sz;
-            inst->regs_written = ret_sz;
+            inst->size_written = ret_sz * REG_SIZE;
             inst->header_size = header_sz;
             inst->predicate = pred;
 
@@ -221,7 +221,7 @@ namespace brw {
                           emit_insert(bld, addr, dims, has_simd4x2),
                           has_simd4x2 ? 1 : dims,
                           emit_insert(bld, src_reg(srcs), size, has_simd4x2),
-                          has_simd4x2 ? 1 : size,
+                          has_simd4x2 && size ? 1 : size,
                           surface, op, rsize, pred);
       }
 
@@ -235,7 +235,7 @@ namespace brw {
             const vec4_builder ubld = bld.exec_all();
             const dst_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD);
 
-            ubld.MOV(dst, src_reg(0));
+            ubld.MOV(dst, brw_imm_d(0));
 
             if (bld.shader->devinfo->gen == 7 &&
                 !bld.shader->devinfo->is_haswell) {
@@ -243,7 +243,7 @@ namespace brw {
                 * have no SIMD4x2 variant.  We only use the two X channels
                 * in that case, mask everything else out.
                 */
-               ubld.MOV(writemask(dst, WRITEMASK_W), src_reg(0x11));
+               ubld.MOV(writemask(dst, WRITEMASK_W), brw_imm_d(0x11));
             }
 
             return src_reg(dst);