}
return size;
case GLSL_TYPE_SAMPLER:
- /* Samplers take up one slot in UNIFORMS[], but they're baked in
- * at link time.
+ /* Samplers take up no register space, since they're baked in at
+ * link time.
*/
- return 1;
+ return 0;
case GLSL_TYPE_ATOMIC_UINT:
return 0;
case GLSL_TYPE_IMAGE:
*predicate = BRW_PREDICATE_NORMAL;
- if (expr) {
- src_reg op[2];
+ if (expr && expr->operation != ir_binop_ubo_load) {
+ src_reg op[3];
vec4_instruction *inst;
- assert(expr->get_num_operands() <= 2);
+ assert(expr->get_num_operands() <= 3);
for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
expr->operands[i]->accept(this);
op[i] = this->result;
brw_conditional_for_comparison(expr->operation)));
break;
+ case ir_triop_csel: {
+ /* Expand the boolean condition into the flag register. */
+ inst = emit(MOV(dst_null_d(), op[0]));
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
+
+ /* Select which boolean to return. */
+ dst_reg temp(this, expr->operands[1]->type);
+ inst = emit(BRW_OPCODE_SEL, temp, op[1], op[2]);
+ inst->predicate = BRW_PREDICATE_NORMAL;
+
+ /* Expand the result to a condition code. */
+ inst = emit(MOV(dst_null_d(), src_reg(temp)));
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ break;
+ }
+
default:
unreachable("not reached");
}
{
ir_expression *expr = ir->condition->as_expression();
- if (expr) {
- src_reg op[2];
+ if (expr && expr->operation != ir_binop_ubo_load) {
+ src_reg op[3];
dst_reg temp;
- assert(expr->get_num_operands() <= 2);
+ assert(expr->get_num_operands() <= 3);
for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
expr->operands[i]->accept(this);
op[i] = this->result;
emit(IF(BRW_PREDICATE_ALIGN16_ANY4H));
return;
+ case ir_triop_csel: {
+ /* Expand the boolean condition into the flag register. */
+ vec4_instruction *inst = emit(MOV(dst_null_d(), op[0]));
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
+
+ /* Select which boolean to return. */
+ dst_reg temp(this, expr->operands[1]->type);
+ inst = emit(BRW_OPCODE_SEL, temp, op[1], op[2]);
+ inst->predicate = BRW_PREDICATE_NORMAL;
+
+ emit(IF(src_reg(temp), src_reg(0), BRW_CONDITIONAL_NZ));
+ return;
+ }
+
default:
unreachable("not reached");
}
* ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
* variables, so no need for them to be in variable_ht.
*
- * Atomic counters take no uniform storage, no need to do
- * anything here.
+ * Some uniforms, such as samplers and atomic counters, have no actual
+ * storage, so we should ignore them.
*/
- if (ir->is_in_uniform_block() || ir->type->contains_atomic())
+ if (ir->is_in_uniform_block() || type_size(ir->type) == 0)
return;
/* Track how big the whole uniform variable is, in case we need to put a
}
}
-bool
-vec4_visitor::try_emit_sat(ir_expression *ir)
-{
- ir_rvalue *sat_src = ir->as_rvalue_to_saturate();
- if (!sat_src)
- return false;
-
- sat_src->accept(this);
- src_reg src = this->result;
-
- this->result = src_reg(this, ir->type);
- vec4_instruction *inst;
- inst = emit(MOV(dst_reg(this->result), src));
- inst->saturate = true;
-
- return true;
-}
-
bool
vec4_visitor::try_emit_mad(ir_expression *ir)
{
bool
vec4_visitor::try_emit_b2f_of_compare(ir_expression *ir)
{
+ /* This optimization relies on CMP setting the destination to 0 when
+ * false. Early hardware only sets the least significant bit, and
+ * leaves the other bits undefined. So we can't use it.
+ */
+ if (brw->gen < 6)
+ return false;
+
ir_expression *const cmp = ir->operands[0]->as_expression();
if (cmp == NULL)
dst_reg result_dst;
vec4_instruction *inst;
- if (try_emit_sat(ir))
- return;
-
if (ir->operation == ir_binop_add) {
if (try_emit_mad(ir))
return;
switch (ir->operation) {
case ir_unop_logic_not:
- /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
- * ones complement of the whole register, not just bit 0.
- */
- emit(XOR(result_dst, op[0], src_reg(1)));
+ if (ctx->Const.UniformBooleanTrue != 1) {
+ emit(NOT(result_dst, op[0]));
+ } else {
+ emit(XOR(result_dst, op[0], src_reg(1)));
+ }
break;
case ir_unop_neg:
op[0].negate = !op[0].negate;
case ir_unop_find_lsb:
emit(FBL(result_dst, op[0]));
break;
+ case ir_unop_saturate:
+ inst = emit(MOV(result_dst, op[0]));
+ inst->saturate = true;
+ break;
case ir_unop_noise:
unreachable("not reached: should be handled by lower_noise");
case ir_binop_nequal: {
emit(CMP(result_dst, op[0], op[1],
brw_conditional_for_comparison(ir->operation)));
- emit(AND(result_dst, result_src, src_reg(0x1)));
+ if (ctx->Const.UniformBooleanTrue == 1) {
+ emit(AND(result_dst, result_src, src_reg(1)));
+ }
break;
}
ir->operands[1]->type->is_vector()) {
emit(CMP(dst_null_d(), op[0], op[1], BRW_CONDITIONAL_Z));
emit(MOV(result_dst, src_reg(0)));
- inst = emit(MOV(result_dst, src_reg(1)));
+ inst = emit(MOV(result_dst, src_reg(ctx->Const.UniformBooleanTrue)));
inst->predicate = BRW_PREDICATE_ALIGN16_ALL4H;
} else {
emit(CMP(result_dst, op[0], op[1], BRW_CONDITIONAL_Z));
- emit(AND(result_dst, result_src, src_reg(0x1)));
+ if (ctx->Const.UniformBooleanTrue == 1) {
+ emit(AND(result_dst, result_src, src_reg(1)));
+ }
}
break;
case ir_binop_any_nequal:
emit(CMP(dst_null_d(), op[0], op[1], BRW_CONDITIONAL_NZ));
emit(MOV(result_dst, src_reg(0)));
- inst = emit(MOV(result_dst, src_reg(1)));
+ inst = emit(MOV(result_dst, src_reg(ctx->Const.UniformBooleanTrue)));
inst->predicate = BRW_PREDICATE_ALIGN16_ANY4H;
} else {
emit(CMP(result_dst, op[0], op[1], BRW_CONDITIONAL_NZ));
- emit(AND(result_dst, result_src, src_reg(0x1)));
+ if (ctx->Const.UniformBooleanTrue == 1) {
+ emit(AND(result_dst, result_src, src_reg(1)));
+ }
}
break;
emit(CMP(dst_null_d(), op[0], src_reg(0), BRW_CONDITIONAL_NZ));
emit(MOV(result_dst, src_reg(0)));
- inst = emit(MOV(result_dst, src_reg(1)));
+ inst = emit(MOV(result_dst, src_reg(ctx->Const.UniformBooleanTrue)));
inst->predicate = BRW_PREDICATE_ALIGN16_ANY4H;
break;
case ir_unop_i2u:
case ir_unop_u2i:
case ir_unop_u2f:
- case ir_unop_b2f:
- case ir_unop_b2i:
case ir_unop_f2i:
case ir_unop_f2u:
emit(MOV(result_dst, op[0]));
break;
+ case ir_unop_b2i:
+ if (ctx->Const.UniformBooleanTrue != 1) {
+ emit(AND(result_dst, op[0], src_reg(1)));
+ } else {
+ emit(MOV(result_dst, op[0]));
+ }
+ break;
+ case ir_unop_b2f:
+ if (ctx->Const.UniformBooleanTrue != 1) {
+ op[0].type = BRW_REGISTER_TYPE_UD;
+ result_dst.type = BRW_REGISTER_TYPE_UD;
+ emit(AND(result_dst, op[0], src_reg(0x3f800000u)));
+ result_dst.type = BRW_REGISTER_TYPE_F;
+ } else {
+ emit(MOV(result_dst, op[0]));
+ }
+ break;
case ir_unop_f2b:
- case ir_unop_i2b: {
+ case ir_unop_i2b:
emit(CMP(result_dst, op[0], src_reg(0.0f), BRW_CONDITIONAL_NZ));
- emit(AND(result_dst, result_src, src_reg(1)));
+ if (ctx->Const.UniformBooleanTrue == 1) {
+ emit(AND(result_dst, result_src, src_reg(1)));
+ }
break;
- }
case ir_unop_trunc:
emit(RNDZ(result_dst, op[0]));
const_offset % 16 / 4,
const_offset % 16 / 4);
- /* UBO bools are any nonzero int. We store bools as either 0 or 1. */
+ /* UBO bools are any nonzero int. We need to convert them to use the
+ * value of true stored in ctx->Const.UniformBooleanTrue.
+ */
if (ir->type->base_type == GLSL_TYPE_BOOL) {
emit(CMP(result_dst, packed_consts, src_reg(0u),
BRW_CONDITIONAL_NZ));
- emit(AND(result_dst, result, src_reg(0x1)));
+ if (ctx->Const.UniformBooleanTrue == 1) {
+ emit(AND(result_dst, result, src_reg(1)));
+ }
} else {
emit(MOV(result_dst, packed_consts));
}
emit(MOV(*dst, src_reg(ir->value.u[i])));
break;
case GLSL_TYPE_BOOL:
- emit(MOV(*dst, src_reg(ir->value.b[i])));
+ emit(MOV(*dst,
+ src_reg(ir->value.b[i] != 0 ? ctx->Const.UniformBooleanTrue
+ : 0)));
break;
default:
unreachable("Non-float/uint/int/bool constant");
ir->actual_parameters.get_head());
ir_variable *location = deref->variable_referenced();
unsigned surf_index = (prog_data->base.binding_table.abo_start +
- location->data.atomic.buffer_index);
+ location->data.binding);
/* Calculate the surface offset */
src_reg offset(this, glsl_type::uint_type);
} else if (ir->op == ir_txf_ms) {
emit(MOV(dst_reg(MRF, param_base + 1, sample_index_type, WRITEMASK_X),
sample_index));
- if (brw->gen >= 7)
+ if (brw->gen >= 7) {
/* MCS data is in the first channel of `mcs`, but we need to get it into
* the .y channel of the second vec4 of params, so replicate .x across
* the whole vec4 and then mask off everything except .y
mcs.swizzle = BRW_SWIZZLE_XXXX;
emit(MOV(dst_reg(MRF, param_base + 1, glsl_type::uint_type, WRITEMASK_Y),
mcs));
+ }
inst->mlen++;
} else if (ir->op == ir_txd) {
const glsl_type *type = lod_type;
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