ALU1(FBH)
ALU1(FBL)
ALU1(CBIT)
+ALU3(MAD)
/** Gen4 predicated IF. */
vec4_instruction *
assert(!"should have been lowered by vec_index_to_cond_assign");
break;
+ case ir_triop_fma:
+ op[0] = fix_3src_operand(op[0]);
+ op[1] = fix_3src_operand(op[1]);
+ op[2] = fix_3src_operand(op[2]);
+ /* Note that the instruction's argument order is reversed from GLSL
+ * and the IR.
+ */
+ emit(MAD(result_dst, op[2], op[1], op[0]));
+ break;
+
case ir_triop_lrp:
op[0] = fix_3src_operand(op[0]);
op[1] = fix_3src_operand(op[1]);
}
vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE);
- inst->eot = complete;
+ inst->urb_write_flags = complete ?
+ BRW_URB_WRITE_EOT_COMPLETE : BRW_URB_WRITE_NO_FLAGS;
return inst;
}