*/
#include "brw_vec4.h"
+#include "brw_vs.h"
#include "glsl/ir_uniform.h"
extern "C" {
#include "main/context.h"
vec4_instruction *
vec4_visitor::IF(src_reg src0, src_reg src1, uint32_t condition)
{
- assert(intel->gen >= 6);
+ assert(brw->gen >= 6);
vec4_instruction *inst;
* before before comparison, producing garbage results for floating
* point comparisons.
*/
- if (intel->gen == 4) {
+ if (brw->gen == 4) {
dst.type = src0.type;
if (dst.file == HW_REG)
dst.fixed_hw_reg.type = dst.type;
* can't use.
*/
- if (intel->gen == 7 && src.file != IMM)
+ if (brw->gen == 7 && src.file != IMM)
return src;
dst_reg expanded = dst_reg(this, glsl_type::vec4_type);
return;
}
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
return emit_math1_gen6(opcode, dst, src);
} else {
return emit_math1_gen4(opcode, dst, src);
return;
}
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
return emit_math2_gen6(opcode, dst, src0, src1);
} else {
return emit_math2_gen4(opcode, dst, src0, src1);
void
vec4_visitor::emit_pack_half_2x16(dst_reg dst, src_reg src0)
{
- if (intel->gen < 7)
+ if (brw->gen < 7)
assert(!"ir_unop_pack_half_2x16 should be lowered");
assert(dst.type == BRW_REGISTER_TYPE_UD);
void
vec4_visitor::emit_unpack_half_2x16(dst_reg dst, src_reg src0)
{
- if (intel->gen < 7)
+ if (brw->gen < 7)
assert(!"ir_unop_unpack_half_2x16 should be lowered");
assert(dst.type == BRW_REGISTER_TYPE_F);
{
gl_clip_plane *clip_planes = brw_select_clip_planes(ctx);
- if (intel->gen < 6) {
- /* Pre-Gen6, we compact clip planes. For example, if the user
- * enables just clip planes 0, 1, and 3, we will enable clip planes
- * 0, 1, and 2 in the hardware, and we'll move clip plane 3 to clip
- * plane 2. This simplifies the implementation of the Gen6 clip
- * thread.
- */
- int compacted_clipplane_index = 0;
- for (int i = 0; i < MAX_CLIP_PLANES; ++i) {
- if (!(key->userclip_planes_enabled_gen_4_5 & (1 << i)))
- continue;
-
- this->uniform_vector_size[this->uniforms] = 4;
- this->userplane[compacted_clipplane_index] = dst_reg(UNIFORM, this->uniforms);
- this->userplane[compacted_clipplane_index].type = BRW_REGISTER_TYPE_F;
- for (int j = 0; j < 4; ++j) {
- prog_data->param[this->uniforms * 4 + j] = &clip_planes[i][j];
- }
- ++compacted_clipplane_index;
- ++this->uniforms;
- }
- } else {
- /* In Gen6 and later, we don't compact clip planes, because this
- * simplifies the implementation of gl_ClipDistance.
- */
- for (int i = 0; i < key->nr_userclip_plane_consts; ++i) {
- this->uniform_vector_size[this->uniforms] = 4;
- this->userplane[i] = dst_reg(UNIFORM, this->uniforms);
- this->userplane[i].type = BRW_REGISTER_TYPE_F;
- for (int j = 0; j < 4; ++j) {
- prog_data->param[this->uniforms * 4 + j] = &clip_planes[i][j];
- }
- ++this->uniforms;
+ for (int i = 0; i < key->nr_userclip_plane_consts; ++i) {
+ this->uniform_vector_size[this->uniforms] = 4;
+ this->userplane[i] = dst_reg(UNIFORM, this->uniforms);
+ this->userplane[i].type = BRW_REGISTER_TYPE_F;
+ for (int j = 0; j < 4; ++j) {
+ prog_data->param[this->uniforms * 4 + j] = &clip_planes[i][j];
}
+ ++this->uniforms;
}
}
break;
case ir_unop_f2b:
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
emit(CMP(dst_null_d(), op[0], src_reg(0.0f), BRW_CONDITIONAL_NZ));
} else {
inst = emit(MOV(dst_null_f(), op[0]));
break;
case ir_unop_i2b:
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
emit(CMP(dst_null_d(), op[0], src_reg(0), BRW_CONDITIONAL_NZ));
} else {
inst = emit(MOV(dst_null_d(), op[0]));
resolve_ud_negate(&this->result);
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
vec4_instruction *inst = emit(AND(dst_null_d(),
this->result, src_reg(1)));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
vec4_visitor::try_emit_mad(ir_expression *ir, int mul_arg)
{
/* 3-src instructions were introduced in gen6. */
- if (intel->gen < 6)
+ if (brw->gen < 6)
return false;
/* MAD can only handle floating-point data. */
dst_reg dst, src_reg src0, src_reg src1)
{
/* original gen4 does destination conversion before comparison. */
- if (intel->gen < 5)
+ if (brw->gen < 5)
dst.type = src0.type;
emit(CMP(dst, src0, src1, brw_conditional_for_comparison(op)));
{
vec4_instruction *inst;
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
inst->conditional_mod = conditionalmod;
} else {
break;
case ir_unop_neg:
op[0].negate = !op[0].negate;
- this->result = op[0];
+ emit(MOV(result_dst, op[0]));
break;
case ir_unop_abs:
op[0].abs = true;
op[0].negate = false;
- this->result = op[0];
+ emit(MOV(result_dst, op[0]));
break;
case ir_unop_sign:
* 16 bits, though, we can just emit a single MUL.
*/
if (is_16bit_constant(ir->operands[0])) {
- if (intel->gen < 7)
+ if (brw->gen < 7)
emit(MUL(result_dst, op[0], op[1]));
else
emit(MUL(result_dst, op[1], op[0]));
} else if (is_16bit_constant(ir->operands[1])) {
- if (intel->gen < 7)
+ if (brw->gen < 7)
emit(MUL(result_dst, op[1], op[0]));
else
emit(MUL(result_dst, op[0], op[1]));
bool use_texture_offset = ir->offset != NULL && ir->op != ir_txf;
/* Texel offsets go in the message header; Gen4 also requires headers. */
- inst->header_present = use_texture_offset || intel->gen < 5;
+ inst->header_present = use_texture_offset || brw->gen < 5;
inst->base_mrf = 2;
inst->mlen = inst->header_present + 1; /* always at least one */
inst->sampler = sampler;
int param_base = inst->base_mrf + inst->header_present;
if (ir->op == ir_txs) {
- int writemask = intel->gen == 4 ? WRITEMASK_W : WRITEMASK_X;
+ int writemask = brw->gen == 4 ? WRITEMASK_W : WRITEMASK_X;
emit(MOV(dst_reg(MRF, param_base, lod_type, writemask), lod));
} else {
int i, coord_mask = 0, zero_mask = 0;
/* Load the LOD info */
if (ir->op == ir_tex || ir->op == ir_txl) {
int mrf, writemask;
- if (intel->gen >= 5) {
+ if (brw->gen >= 5) {
mrf = param_base + 1;
if (ir->shadow_comparitor) {
writemask = WRITEMASK_Y;
writemask = WRITEMASK_X;
inst->mlen++;
}
- } else /* intel->gen == 4 */ {
+ } else /* brw->gen == 4 */ {
mrf = param_base;
- writemask = WRITEMASK_Z;
+ writemask = WRITEMASK_W;
}
emit(MOV(dst_reg(MRF, mrf, lod_type, writemask), lod));
} else if (ir->op == ir_txf) {
} else if (ir->op == ir_txd) {
const glsl_type *type = lod_type;
- if (intel->gen >= 5) {
+ if (brw->gen >= 5) {
dPdx.swizzle = BRW_SWIZZLE4(SWIZZLE_X,SWIZZLE_X,SWIZZLE_Y,SWIZZLE_Y);
dPdy.swizzle = BRW_SWIZZLE4(SWIZZLE_X,SWIZZLE_X,SWIZZLE_Y,SWIZZLE_Y);
emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_XZ), dPdx));
shadow_comparitor));
}
}
- } else /* intel->gen == 4 */ {
+ } else /* brw->gen == 4 */ {
emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_XYZ), dPdx));
emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_XYZ), dPdy));
inst->mlen += 2;
}
int zero_mask = 0, one_mask = 0, copy_mask = 0;
- int swizzle[4];
+ int swizzle[4] = {0};
for (int i = 0; i < 4; i++) {
switch (GET_SWZ(s, i)) {
*/
this->base_ir = ir->condition;
- if (intel->gen == 6) {
+ if (brw->gen == 6) {
emit_if_gen6(ir);
} else {
uint32_t predicate;
emit(BRW_OPCODE_ENDIF);
}
+void
+vec4_visitor::visit(ir_emit_vertex *)
+{
+ assert(!"not reached");
+}
+
+void
+vec4_visitor::visit(ir_end_primitive *)
+{
+ assert(!"not reached");
+}
+
void
vec4_visitor::emit_ndc_computation()
{
void
vec4_visitor::emit_psiz_and_flags(struct brw_reg reg)
{
- if (intel->gen < 6 &&
+ if (brw->gen < 6 &&
((prog_data->vue_map.slots_valid & VARYING_BIT_PSIZ) ||
key->userclip_active || brw->has_negative_rhw_bug)) {
dst_reg header1 = dst_reg(this, glsl_type::uvec4_type);
dst_reg header1_w = header1;
header1_w.writemask = WRITEMASK_W;
- GLuint i;
emit(MOV(header1, 0u));
emit(AND(header1_w, src_reg(header1_w), 0x7ff << 8));
}
- current_annotation = "Clipping flags";
- for (i = 0; i < key->nr_userclip_plane_consts; i++) {
- vec4_instruction *inst;
- gl_varying_slot slot = (prog_data->vue_map.slots_valid & VARYING_BIT_CLIP_VERTEX)
- ? VARYING_SLOT_CLIP_VERTEX : VARYING_SLOT_POS;
+ if (key->userclip_active) {
+ current_annotation = "Clipping flags";
+ dst_reg flags0 = dst_reg(this, glsl_type::uint_type);
+ dst_reg flags1 = dst_reg(this, glsl_type::uint_type);
- inst = emit(DP4(dst_null_f(), src_reg(output_reg[slot]),
- src_reg(this->userplane[i])));
- inst->conditional_mod = BRW_CONDITIONAL_L;
+ emit(CMP(dst_null_f(), src_reg(output_reg[VARYING_SLOT_CLIP_DIST0]), src_reg(0.0f), BRW_CONDITIONAL_L));
+ emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2, flags0, src_reg(0));
+ emit(OR(header1_w, src_reg(header1_w), src_reg(flags0)));
- inst = emit(OR(header1_w, src_reg(header1_w), 1u << i));
- inst->predicate = BRW_PREDICATE_NORMAL;
+ emit(CMP(dst_null_f(), src_reg(output_reg[VARYING_SLOT_CLIP_DIST1]), src_reg(0.0f), BRW_CONDITIONAL_L));
+ emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2, flags1, src_reg(0));
+ emit(SHL(flags1, src_reg(flags1), src_reg(4)));
+ emit(OR(header1_w, src_reg(header1_w), src_reg(flags1)));
}
/* i965 clipping workaround:
}
emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), src_reg(header1)));
- } else if (intel->gen < 6) {
+ } else if (brw->gen < 6) {
emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), 0u));
} else {
emit(MOV(retype(reg, BRW_REGISTER_TYPE_D), src_reg(0)));
}
void
-vec4_visitor::emit_clip_distances(struct brw_reg reg, int offset)
+vec4_visitor::emit_clip_distances(dst_reg reg, int offset)
{
- if (intel->gen < 6) {
- /* Clip distance slots are set aside in gen5, but they are not used. It
- * is not clear whether we actually need to set aside space for them,
- * but the performance cost is negligible.
- */
- return;
- }
-
/* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
*
* "If a linked set of shaders forming the vertex stage contains no
for (int i = 0; i + offset < key->nr_userclip_plane_consts && i < 4;
++i) {
- emit(DP4(dst_reg(brw_writemask(reg, 1 << i)),
+ reg.writemask = 1 << i;
+ emit(DP4(reg,
src_reg(output_reg[clip_vertex]),
src_reg(this->userplane[i + offset])));
}
current_annotation = "gl_Position";
emit(MOV(reg, src_reg(output_reg[VARYING_SLOT_POS])));
break;
- case VARYING_SLOT_CLIP_DIST0:
- case VARYING_SLOT_CLIP_DIST1:
- if (this->key->uses_clip_distance) {
- emit_generic_urb_slot(reg, varying);
- } else {
- current_annotation = "user clip distances";
- emit_clip_distances(hw_reg, (varying - VARYING_SLOT_CLIP_DIST0) * 4);
- }
- break;
case VARYING_SLOT_EDGE:
/* This is present when doing unfilled polygons. We're supposed to copy
* the edge flag from the user-provided vertex array
static int
align_interleaved_urb_mlen(struct brw_context *brw, int mlen)
{
- struct intel_context *intel = &brw->intel;
-
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
/* URB data written (does not include the message header reg) must
* be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
* section 5.4.3.2.2: URB_INTERLEAVED.
*/
emit_urb_write_header(mrf++);
- if (intel->gen < 6) {
+ if (brw->gen < 6) {
emit_ndc_computation();
}
+ /* Lower legacy ff and ClipVertex clipping to clip distances */
+ if (key->userclip_active && !key->uses_clip_distance) {
+ current_annotation = "user clip distances";
+
+ output_reg[VARYING_SLOT_CLIP_DIST0] = dst_reg(this, glsl_type::vec4_type);
+ output_reg[VARYING_SLOT_CLIP_DIST1] = dst_reg(this, glsl_type::vec4_type);
+
+ emit_clip_distances(output_reg[VARYING_SLOT_CLIP_DIST0], 0);
+ emit_clip_distances(output_reg[VARYING_SLOT_CLIP_DIST1], 4);
+ }
+
/* Set up the VUE data for the first URB write */
int slot;
for (slot = 0; slot < prog_data->vue_map.num_slots; ++slot) {
/* Pre-gen6, the message header uses byte offsets instead of vec4
* (16-byte) offset units.
*/
- if (intel->gen < 6)
+ if (brw->gen < 6)
message_header_scale *= 16;
if (reladdr) {
/* Pre-gen6, the message header uses byte offsets instead of vec4
* (16-byte) offset units.
*/
- if (intel->gen < 6) {
+ if (brw->gen < 6) {
emit_before(inst, MUL(dst_reg(index), index, src_reg(16)));
}
return index;
} else {
- int message_header_scale = intel->gen < 6 ? 16 : 1;
+ int message_header_scale = brw->gen < 6 ? 16 : 1;
return src_reg(reg_offset * message_header_scale);
}
}
src_reg offset = get_pull_constant_offset(inst, orig_src.reladdr, reg_offset);
vec4_instruction *load;
- if (intel->gen >= 7) {
+ if (brw->gen >= 7) {
dst_reg grf_offset = dst_reg(this, glsl_type::int_type);
grf_offset.type = offset.type;
emit_before(inst, MOV(grf_offset, offset));
: debug_flag(debug_flag)
{
this->brw = brw;
- this->intel = &brw->intel;
- this->ctx = &intel->ctx;
+ this->ctx = &brw->ctx;
this->shader_prog = shader_prog;
this->shader = shader;
this->virtual_grf_array_size = 0;
this->live_intervals_valid = false;
- this->max_grf = intel->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
+ this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
this->uniforms = 0;
}