ALU1(FBH)
ALU1(FBL)
ALU1(CBIT)
+ALU3(MAD)
/** Gen4 predicated IF. */
vec4_instruction *
emit(IF(this->result, src_reg(0), BRW_CONDITIONAL_NZ));
}
-static dst_reg
+dst_reg
with_writemask(dst_reg const & r, int mask)
{
dst_reg result = r;
src_reg packed_consts = src_reg(this, glsl_type::vec4_type);
packed_consts.type = result.type;
src_reg surf_index =
- src_reg(SURF_INDEX_VS_UBO(uniform_block->value.u[0]));
+ src_reg(SURF_INDEX_VEC4_UBO(uniform_block->value.u[0]));
if (const_offset_ir) {
offset = src_reg(const_offset / 16);
} else {
assert(!"should have been lowered by vec_index_to_cond_assign");
break;
+ case ir_triop_fma:
+ op[0] = fix_3src_operand(op[0]);
+ op[1] = fix_3src_operand(op[1]);
+ op[2] = fix_3src_operand(op[2]);
+ /* Note that the instruction's argument order is reversed from GLSL
+ * and the IR.
+ */
+ emit(MAD(result_dst, op[2], op[1], op[0]));
+ break;
+
case ir_triop_lrp:
op[0] = fix_3src_operand(op[0]);
op[1] = fix_3src_operand(op[1]);
}
vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE);
- inst->eot = complete;
+ inst->urb_write_flags = complete ?
+ BRW_URB_WRITE_EOT_COMPLETE : BRW_URB_WRITE_NO_FLAGS;
return inst;
}
int base_offset)
{
int reg_offset = base_offset + orig_src.reg_offset;
- src_reg index = src_reg((unsigned)SURF_INDEX_VERT_CONST_BUFFER);
+ src_reg index = src_reg((unsigned)SURF_INDEX_VEC4_CONST_BUFFER);
src_reg offset = get_pull_constant_offset(inst, orig_src.reladdr, reg_offset);
vec4_instruction *load;