i965/vec4: Make with_writemask() non-static.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_visitor.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index fa32e4a6848dea037511c3c55daf2aa8e4075dd1..e3bbf91aad686c2155613828447389f9f535115c 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -22,6 +22,7 @@
  */
 
 #include "brw_vec4.h"
+#include "brw_vs.h"
 #include "glsl/ir_uniform.h"
 extern "C" {
 #include "main/context.h"
@@ -143,6 +144,7 @@ ALU3(BFI2)
 ALU1(FBH)
 ALU1(FBL)
 ALU1(CBIT)
+ALU3(MAD)
 
 /** Gen4 predicated IF. */
 vec4_instruction *
@@ -662,40 +664,14 @@ vec4_visitor::setup_uniform_clipplane_values()
 {
    gl_clip_plane *clip_planes = brw_select_clip_planes(ctx);
 
-   if (brw->gen < 6) {
-      /* Pre-Gen6, we compact clip planes.  For example, if the user
-       * enables just clip planes 0, 1, and 3, we will enable clip planes
-       * 0, 1, and 2 in the hardware, and we'll move clip plane 3 to clip
-       * plane 2.  This simplifies the implementation of the Gen6 clip
-       * thread.
-       */
-      int compacted_clipplane_index = 0;
-      for (int i = 0; i < MAX_CLIP_PLANES; ++i) {
-        if (!(key->userclip_planes_enabled_gen_4_5 & (1 << i)))
-           continue;
-
-        this->uniform_vector_size[this->uniforms] = 4;
-        this->userplane[compacted_clipplane_index] = dst_reg(UNIFORM, this->uniforms);
-        this->userplane[compacted_clipplane_index].type = BRW_REGISTER_TYPE_F;
-        for (int j = 0; j < 4; ++j) {
-           prog_data->param[this->uniforms * 4 + j] = &clip_planes[i][j];
-        }
-        ++compacted_clipplane_index;
-        ++this->uniforms;
-      }
-   } else {
-      /* In Gen6 and later, we don't compact clip planes, because this
-       * simplifies the implementation of gl_ClipDistance.
-       */
-      for (int i = 0; i < key->nr_userclip_plane_consts; ++i) {
-        this->uniform_vector_size[this->uniforms] = 4;
-        this->userplane[i] = dst_reg(UNIFORM, this->uniforms);
-        this->userplane[i].type = BRW_REGISTER_TYPE_F;
-        for (int j = 0; j < 4; ++j) {
-           prog_data->param[this->uniforms * 4 + j] = &clip_planes[i][j];
-        }
-        ++this->uniforms;
+   for (int i = 0; i < key->nr_userclip_plane_consts; ++i) {
+      this->uniform_vector_size[this->uniforms] = 4;
+      this->userplane[i] = dst_reg(UNIFORM, this->uniforms);
+      this->userplane[i].type = BRW_REGISTER_TYPE_F;
+      for (int j = 0; j < 4; ++j) {
+         prog_data->param[this->uniforms * 4 + j] = &clip_planes[i][j];
       }
+      ++this->uniforms;
    }
 }
 
@@ -932,7 +908,7 @@ vec4_visitor::emit_if_gen6(ir_if *ir)
    emit(IF(this->result, src_reg(0), BRW_CONDITIONAL_NZ));
 }
 
-static dst_reg
+dst_reg
 with_writemask(dst_reg const & r, int mask)
 {
    dst_reg result = r;
@@ -1391,12 +1367,12 @@ vec4_visitor::visit(ir_expression *ir)
       break;
    case ir_unop_neg:
       op[0].negate = !op[0].negate;
-      this->result = op[0];
+      emit(MOV(result_dst, op[0]));
       break;
    case ir_unop_abs:
       op[0].abs = true;
       op[0].negate = false;
-      this->result = op[0];
+      emit(MOV(result_dst, op[0]));
       break;
 
    case ir_unop_sign:
@@ -1699,7 +1675,7 @@ vec4_visitor::visit(ir_expression *ir)
       src_reg packed_consts = src_reg(this, glsl_type::vec4_type);
       packed_consts.type = result.type;
       src_reg surf_index =
-         src_reg(SURF_INDEX_VS_UBO(uniform_block->value.u[0]));
+         src_reg(SURF_INDEX_VEC4_UBO(uniform_block->value.u[0]));
       if (const_offset_ir) {
          offset = src_reg(const_offset / 16);
       } else {
@@ -1736,6 +1712,16 @@ vec4_visitor::visit(ir_expression *ir)
       assert(!"should have been lowered by vec_index_to_cond_assign");
       break;
 
+   case ir_triop_fma:
+      op[0] = fix_3src_operand(op[0]);
+      op[1] = fix_3src_operand(op[1]);
+      op[2] = fix_3src_operand(op[2]);
+      /* Note that the instruction's argument order is reversed from GLSL
+       * and the IR.
+       */
+      emit(MAD(result_dst, op[2], op[1], op[0]));
+      break;
+
    case ir_triop_lrp:
       op[0] = fix_3src_operand(op[0]);
       op[1] = fix_3src_operand(op[1]);
@@ -2813,7 +2799,8 @@ vec4_vs_visitor::emit_urb_write_opcode(bool complete)
    }
 
    vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE);
-   inst->eot = complete;
+   inst->urb_write_flags = complete ?
+      BRW_URB_WRITE_EOT_COMPLETE : BRW_URB_WRITE_NO_FLAGS;
 
    return inst;
 }
@@ -3112,7 +3099,7 @@ vec4_visitor::emit_pull_constant_load(vec4_instruction *inst,
                                      int base_offset)
 {
    int reg_offset = base_offset + orig_src.reg_offset;
-   src_reg index = src_reg((unsigned)SURF_INDEX_VERT_CONST_BUFFER);
+   src_reg index = src_reg((unsigned)SURF_INDEX_VEC4_CONST_BUFFER);
    src_reg offset = get_pull_constant_offset(inst, orig_src.reladdr, reg_offset);
    vec4_instruction *load;