{
vec4_instruction *inst;
- inst = emit(BRW_OPCODE_CMP, dst_null_d(), src0, src1);
- inst->conditional_mod = conditional_mod;
+ inst = emit(CMP(dst_null_f(), src0, src1, conditional_mod));
inst = emit(BRW_OPCODE_SEL, dst, one, src_reg(0.0f));
inst->predicate = BRW_PREDICATE_NORMAL;
/* if (tmp.y < 0) tmp.y = 0; */
src_reg tmp_y = swizzle(src[0], BRW_SWIZZLE_YYYY);
result.writemask = WRITEMASK_Z;
- emit_minmax(BRW_CONDITIONAL_G, result, tmp_y, src_reg(0.0f));
+ emit_minmax(BRW_CONDITIONAL_GE, result, tmp_y, src_reg(0.0f));
src_reg clamped_y(result);
clamped_y.swizzle = BRW_SWIZZLE_ZZZZ;
}
case OPCODE_MAX:
- emit_minmax(BRW_CONDITIONAL_G, dst, src[0], src[1]);
+ emit_minmax(BRW_CONDITIONAL_GE, dst, src[0], src[1]);
break;
case OPCODE_MIN:
}
/* Copy the temporary back into the actual destination register. */
- if (vpi->Opcode != OPCODE_END) {
+ if (_mesa_num_inst_dst_regs(vpi->Opcode) != 0) {
emit(MOV(get_vp_dst_reg(vpi->DstReg), src_reg(dst)));
}
}
unsigned i;
for (i = 0; i < params->NumParameters * 4; i++) {
stage_prog_data->pull_param[i] =
- ¶ms->ParameterValues[i / 4][i % 4].f;
+ ¶ms->ParameterValues[i / 4][i % 4];
}
stage_prog_data->nr_pull_params = i;
}
this->uniform_vector_size[this->uniforms] = components;
for (unsigned i = 0; i < 4; i++) {
stage_prog_data->param[this->uniforms * 4 + i] = i >= components
- ? 0 : &plist->ParameterValues[p][i].f;
+ ? 0 : &plist->ParameterValues[p][i];
}
this->uniforms++; /* counted in vec4 units */
}
/* Add the small constant index to the address register */
src_reg reladdr = src_reg(this, glsl_type::int_type);
+
+ /* We have to use a message header on Skylake to get SIMD4x2 mode.
+ * Reserve space for the register.
+ */
+ if (brw->gen >= 9) {
+ reladdr.reg_offset++;
+ alloc.sizes[reladdr.reg] = 2;
+ }
+
dst_reg dst_reladdr = dst_reg(reladdr);
dst_reladdr.writemask = WRITEMASK_X;
emit(ADD(dst_reladdr, this->vp_addr_reg, src_reg(src.Index)));
result = src_reg(this, glsl_type::vec4_type);
src_reg surf_index = src_reg(unsigned(prog_data->base.binding_table.pull_constants_start));
- vec4_instruction *load =
- new(mem_ctx) vec4_instruction(this, VS_OPCODE_PULL_CONSTANT_LOAD,
- dst_reg(result), surf_index, reladdr);
- load->base_mrf = 14;
- load->mlen = 1;
+ vec4_instruction *load;
+ if (brw->gen >= 7) {
+ load = new(mem_ctx)
+ vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
+ dst_reg(result), surf_index, reladdr);
+ load->mlen = 1;
+ } else {
+ load = new(mem_ctx)
+ vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD,
+ dst_reg(result), surf_index, reladdr);
+ load->base_mrf = 14;
+ load->mlen = 1;
+ }
emit(load);
break;
}