i965/nir/vec4: Prepare source and destination registers for ALU operations

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_vp.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
index 85f2de577fc5fd77fe51b5cf1333063cc784f5e8..d1a72d787e7479ca1a62e6101432dbcf85e9b1dc 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
@@ -43,8 +43,7 @@ vec4_visitor::emit_vp_sop(enum brw_conditional_mod conditional_mod,
 {
    vec4_instruction *inst;
 
-   inst = emit(BRW_OPCODE_CMP, dst_null_d(), src0, src1);
-   inst->conditional_mod = conditional_mod;
+   inst = emit(CMP(dst_null_f(), src0, src1, conditional_mod));
 
    inst = emit(BRW_OPCODE_SEL, dst, one, src_reg(0.0f));
    inst->predicate = BRW_PREDICATE_NORMAL;
@@ -97,7 +96,7 @@ vec4_vs_visitor::emit_program_code()
          break;
 
       case OPCODE_ARL:
-         if (brw->gen >= 6) {
+         if (devinfo->gen >= 6) {
             dst.writemask = WRITEMASK_X;
             dst_reg dst_f = dst;
             dst_f.type = BRW_REGISTER_TYPE_F;
@@ -227,7 +226,7 @@ vec4_vs_visitor::emit_program_code()
                /* if (tmp.y < 0) tmp.y = 0; */
                src_reg tmp_y = swizzle(src[0], BRW_SWIZZLE_YYYY);
                result.writemask = WRITEMASK_Z;
-               emit_minmax(BRW_CONDITIONAL_G, result, tmp_y, src_reg(0.0f));
+               emit_minmax(BRW_CONDITIONAL_GE, result, tmp_y, src_reg(0.0f));
 
                src_reg clamped_y(result);
                clamped_y.swizzle = BRW_SWIZZLE_ZZZZ;
@@ -314,7 +313,7 @@ vec4_vs_visitor::emit_program_code()
       }
 
       case OPCODE_MAX:
-         emit_minmax(BRW_CONDITIONAL_G, dst, src[0], src[1]);
+         emit_minmax(BRW_CONDITIONAL_GE, dst, src[0], src[1]);
          break;
 
       case OPCODE_MIN:
@@ -382,12 +381,11 @@ vec4_vs_visitor::emit_program_code()
          break;
 
       default:
-         _mesa_problem(ctx, "Unsupported opcode %s in vertex program\n",
-                       _mesa_opcode_string(vpi->Opcode));
+         assert(!"Unsupported opcode in vertex program");
       }
 
       /* Copy the temporary back into the actual destination register. */
-      if (vpi->Opcode != OPCODE_END) {
+      if (_mesa_num_inst_dst_regs(vpi->Opcode) != 0) {
          emit(MOV(get_vp_dst_reg(vpi->DstReg), src_reg(dst)));
       }
    }
@@ -396,8 +394,7 @@ vec4_vs_visitor::emit_program_code()
     * pull constants.  Do that now.
     */
    if (this->need_all_constants_in_pull_buffer) {
-      const struct gl_program_parameter_list *params =
-         vs_compile->vp->program.Base.Parameters;
+      const struct gl_program_parameter_list *params = vp->Base.Parameters;
       unsigned i;
       for (i = 0; i < params->NumParameters * 4; i++) {
          stage_prog_data->pull_param[i] =
@@ -417,8 +414,7 @@ vec4_vs_visitor::setup_vp_regs()
       vp_temp_regs[i] = src_reg(this, glsl_type::vec4_type);
 
    /* PROGRAM_STATE_VAR etc. */
-   struct gl_program_parameter_list *plist =
-      vs_compile->vp->program.Base.Parameters;
+   struct gl_program_parameter_list *plist = vp->Base.Parameters;
    for (unsigned p = 0; p < plist->NumParameters; p++) {
       unsigned components = plist->Parameters[p].Size;
 
@@ -488,8 +484,7 @@ vec4_vs_visitor::get_vp_dst_reg(const prog_dst_register &dst)
 src_reg
 vec4_vs_visitor::get_vp_src_reg(const prog_src_register &src)
 {
-   struct gl_program_parameter_list *plist =
-      vs_compile->vp->program.Base.Parameters;
+   struct gl_program_parameter_list *plist = vp->Base.Parameters;
 
    src_reg result;
 
@@ -528,11 +523,12 @@ vec4_vs_visitor::get_vp_src_reg(const prog_src_register &src)
 
          /* Add the small constant index to the address register */
          src_reg reladdr = src_reg(this, glsl_type::int_type);
+
          dst_reg dst_reladdr = dst_reg(reladdr);
          dst_reladdr.writemask = WRITEMASK_X;
          emit(ADD(dst_reladdr, this->vp_addr_reg, src_reg(src.Index)));
 
-         if (brw->gen < 6)
+         if (devinfo->gen < 6)
             emit(MUL(dst_reladdr, reladdr, src_reg(16)));
 
       #if 0
@@ -545,19 +541,11 @@ vec4_vs_visitor::get_vp_src_reg(const prog_src_register &src)
 
          result = src_reg(this, glsl_type::vec4_type);
          src_reg surf_index = src_reg(unsigned(prog_data->base.binding_table.pull_constants_start));
-         vec4_instruction *load;
-         if (brw->gen >= 7) {
-            load = new(mem_ctx)
-               vec4_instruction(this, VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
-                                dst_reg(result), surf_index, reladdr);
-         } else {
-            load = new(mem_ctx)
-               vec4_instruction(this, VS_OPCODE_PULL_CONSTANT_LOAD,
-                                dst_reg(result), surf_index, reladdr);
-            load->base_mrf = 14;
-            load->mlen = 1;
-         }
-         emit(load);
+
+         emit_pull_constant_load_reg(dst_reg(result),
+                                     surf_index,
+                                     reladdr,
+                                     NULL, NULL /* before_block/inst */);
          break;
       }
 
@@ -582,15 +570,13 @@ vec4_vs_visitor::get_vp_src_reg(const prog_src_register &src)
          break;
 
       default:
-         _mesa_problem(ctx, "bad uniform src register file: %s\n",
-                       _mesa_register_file_name((gl_register_file)src.File));
+         assert(!"Bad uniform in src register file");
          return src_reg(this, glsl_type::vec4_type);
       }
       break;
 
    default:
-      _mesa_problem(ctx, "bad src register file: %s\n",
-                    _mesa_register_file_name((gl_register_file)src.File));
+      assert(!"Bad src register file");
       return src_reg(this, glsl_type::vec4_type);
    }