#include "main/macros.h"
-#include "shader/program.h"
-#include "shader/prog_parameter.h"
-#include "shader/prog_print.h"
+#include "program/program.h"
+#include "program/prog_parameter.h"
+#include "program/prog_print.h"
#include "brw_context.h"
#include "brw_vs.h"
+/* Return the SrcReg index of the channels that can be immediate float operands
+ * instead of usage of PROGRAM_CONSTANT values through push/pull.
+ */
+static GLboolean
+brw_vs_arg_can_be_immediate(enum prog_opcode opcode, int arg)
+{
+ int opcode_array[] = {
+ [OPCODE_ADD] = 2,
+ [OPCODE_CMP] = 3,
+ [OPCODE_DP3] = 2,
+ [OPCODE_DP4] = 2,
+ [OPCODE_DPH] = 2,
+ [OPCODE_MAX] = 2,
+ [OPCODE_MIN] = 2,
+ [OPCODE_MUL] = 2,
+ [OPCODE_SEQ] = 2,
+ [OPCODE_SGE] = 2,
+ [OPCODE_SGT] = 2,
+ [OPCODE_SLE] = 2,
+ [OPCODE_SLT] = 2,
+ [OPCODE_SNE] = 2,
+ [OPCODE_XPD] = 2,
+ };
+
+ /* These opcodes get broken down in a way that allow two
+ * args to be immediates.
+ */
+ if (opcode == OPCODE_MAD || opcode == OPCODE_LRP) {
+ if (arg == 1 || arg == 2)
+ return GL_TRUE;
+ }
+
+ if (opcode > ARRAY_SIZE(opcode_array))
+ return GL_FALSE;
+
+ return arg == opcode_array[opcode] - 1;
+}
static struct brw_reg get_tmp( struct brw_vs_compile *c )
{
c->first_output = reg;
c->first_overflow_output = 0;
- if (intel->is_ironlake)
- mrf = 8;
+ if (intel->gen >= 6)
+ mrf = 4;
+ else if (intel->gen == 5)
+ mrf = 8;
else
- mrf = 4;
+ mrf = 4;
for (i = 0; i < VERT_RESULT_MAX; i++) {
if (c->prog_data.outputs_written & BITFIELD64_BIT(i)) {
mrf++; /* just a placeholder? XXX fix later stages & remove this */
}
else {
- if (mrf < 16) {
+ /* Two restrictions on our compute-to-MRF here. The
+ * message length for all SEND messages is restricted to
+ * [1,15], so we can't use mrf 15, as that means a length
+ * of 16.
+ *
+ * Additionally, URB writes are aligned to URB rows, so we
+ * need to put an even number of registers of URB data in
+ * each URB write so that the later write is aligned. A
+ * message length of 15 means 1 message header reg plus 14
+ * regs of URB data.
+ *
+ * For attributes beyond the compute-to-MRF, we compute to
+ * GRFs and they will be written in the second URB_WRITE.
+ */
+ if (mrf < 15) {
c->regs[PROGRAM_OUTPUT][i] = brw_message_reg(mrf);
mrf++;
}
else {
- /* too many vertex results to fit in MRF, use GRF for overflow */
if (!c->first_overflow_output)
c->first_overflow_output = i;
c->regs[PROGRAM_OUTPUT][i] = brw_vec8_grf(reg, 0);
*/
attributes_in_vue = MAX2(c->nr_outputs, c->nr_inputs);
- if (intel->is_ironlake)
- c->prog_data.urb_entry_size = (attributes_in_vue + 6 + 3) / 4;
+ /* See emit_vertex_write() for where the VUE's overhead on top of the
+ * attributes comes from.
+ */
+ if (intel->gen >= 6)
+ c->prog_data.urb_entry_size = (attributes_in_vue + 2 + 7) / 8;
+ else if (intel->gen == 5)
+ c->prog_data.urb_entry_size = (attributes_in_vue + 6 + 3) / 4;
else
- c->prog_data.urb_entry_size = (attributes_in_vue + 2 + 3) / 4;
+ c->prog_data.urb_entry_size = (attributes_in_vue + 2 + 3) / 4;
c->prog_data.total_grf = reg;
if (INTEL_DEBUG & DEBUG_VS) {
- _mesa_printf("%s NumAddrRegs %d\n", __FUNCTION__, c->vp->program.Base.NumAddressRegs);
- _mesa_printf("%s NumTemps %d\n", __FUNCTION__, c->vp->program.Base.NumTemporaries);
- _mesa_printf("%s reg = %d\n", __FUNCTION__, reg);
+ printf("%s NumAddrRegs %d\n", __FUNCTION__, c->vp->program.Base.NumAddressRegs);
+ printf("%s NumTemps %d\n", __FUNCTION__, c->vp->program.Base.NumTemporaries);
+ printf("%s reg = %d\n", __FUNCTION__, reg);
}
}
struct brw_reg arg0,
struct brw_reg arg1 )
{
- brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, arg0, arg1);
- brw_SEL(p, dst, arg1, arg0);
+ brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_GE, arg0, arg1);
+ brw_SEL(p, dst, arg0, arg1);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
}
* whether that turns out to be a simulator bug or not:
*/
struct brw_compile *p = &c->func;
+ struct intel_context *intel = &p->brw->intel;
struct brw_reg tmp = dst;
- GLboolean need_tmp = (dst.dw1.bits.writemask != 0xf ||
- dst.file != BRW_GENERAL_REGISTER_FILE);
+ GLboolean need_tmp = (intel->gen < 6 &&
+ (dst.dw1.bits.writemask != 0xf ||
+ dst.file != BRW_GENERAL_REGISTER_FILE));
if (need_tmp)
tmp = get_tmp(c);
GLuint precision)
{
struct brw_compile *p = &c->func;
+ struct intel_context *intel = &p->brw->intel;
struct brw_reg tmp = dst;
- GLboolean need_tmp = (dst.dw1.bits.writemask != 0xf ||
- dst.file != BRW_GENERAL_REGISTER_FILE);
+ GLboolean need_tmp = (intel->gen < 6 &&
+ (dst.dw1.bits.writemask != 0xf ||
+ dst.file != BRW_GENERAL_REGISTER_FILE));
if (need_tmp)
tmp = get_tmp(c);
const GLint index = inst->SrcReg[argIndex].Index;
const GLboolean relAddr = inst->SrcReg[argIndex].RelAddr;
+ if (brw_vs_arg_can_be_immediate(inst->Opcode, argIndex)) {
+ const struct prog_src_register *src = &inst->SrcReg[argIndex];
+
+ if (src->Swizzle == MAKE_SWIZZLE4(SWIZZLE_ZERO,
+ SWIZZLE_ZERO,
+ SWIZZLE_ZERO,
+ SWIZZLE_ZERO)) {
+ return brw_imm_f(0.0f);
+ } else if (src->Swizzle == MAKE_SWIZZLE4(SWIZZLE_ONE,
+ SWIZZLE_ONE,
+ SWIZZLE_ONE,
+ SWIZZLE_ONE)) {
+ if (src->Negate)
+ return brw_imm_f(-1.0F);
+ else
+ return brw_imm_f(1.0F);
+ } else if (src->File == PROGRAM_CONSTANT) {
+ const struct gl_program_parameter_list *params;
+ float f;
+ int component = -1;
+
+ switch (src->Swizzle) {
+ case SWIZZLE_XXXX:
+ component = 0;
+ break;
+ case SWIZZLE_YYYY:
+ component = 1;
+ break;
+ case SWIZZLE_ZZZZ:
+ component = 2;
+ break;
+ case SWIZZLE_WWWW:
+ component = 3;
+ break;
+ }
+
+ if (component >= 0) {
+ params = c->vp->program.Base.Parameters;
+ f = params->ParameterValues[src->Index][component];
+
+ if (src->Abs)
+ f = fabs(f);
+ if (src->Negate)
+ f = -f;
+ return brw_imm_f(f);
+ }
+ }
+ }
+
switch (file) {
case PROGRAM_TEMPORARY:
case PROGRAM_INPUT:
struct brw_reg pos = c->regs[PROGRAM_OUTPUT][VERT_RESULT_HPOS];
struct brw_reg ndc;
int eot;
- GLuint len_vertext_header = 2;
+ GLuint len_vertex_header = 2;
if (c->key.copy_edgeflag) {
brw_MOV(p,
get_reg(c, PROGRAM_INPUT, VERT_ATTRIB_EDGEFLAG));
}
- /* Build ndc coords */
- ndc = get_tmp(c);
- /* ndc = 1.0 / pos.w */
- emit_math1(c, BRW_MATH_FUNCTION_INV, ndc, brw_swizzle1(pos, 3), BRW_MATH_PRECISION_FULL);
- /* ndc.xyz = pos * ndc */
- brw_MUL(p, brw_writemask(ndc, WRITEMASK_XYZ), pos, ndc);
+ if (intel->gen < 6) {
+ /* Build ndc coords */
+ ndc = get_tmp(c);
+ /* ndc = 1.0 / pos.w */
+ emit_math1(c, BRW_MATH_FUNCTION_INV, ndc, brw_swizzle1(pos, 3), BRW_MATH_PRECISION_FULL);
+ /* ndc.xyz = pos * ndc */
+ brw_MUL(p, brw_writemask(ndc, WRITEMASK_XYZ), pos, ndc);
+ }
/* Update the header for point size, user clipping flags, and -ve rhw
* workaround.
* of zeros followed by two sets of NDC coordinates:
*/
brw_set_access_mode(p, BRW_ALIGN_1);
- brw_MOV(p, offset(m0, 2), ndc);
-
- if (intel->is_ironlake) {
- /* There are 20 DWs (D0-D19) in VUE vertex header on Ironlake */
- brw_MOV(p, offset(m0, 3), pos); /* a portion of vertex header */
- /* m4, m5 contain the distances from vertex to the user clip planeXXX.
- * Seems it is useless for us.
- * m6 is used for aligning, so that the remainder of vertex element is
- * reg-aligned.
- */
- brw_MOV(p, offset(m0, 7), pos); /* the remainder of vertex element */
- len_vertext_header = 6;
+
+ /* The VUE layout is documented in Volume 2a. */
+ if (intel->gen >= 6) {
+ /* There are 8 or 16 DWs (D0-D15) in VUE header on Sandybridge:
+ * dword 0-3 (m1) of the header is indices, point width, clip flags.
+ * dword 4-7 (m2) is the 4D space position
+ * dword 8-15 (m3,m4) of the vertex header is the user clip distance if
+ * enabled. We don't use it, so skip it.
+ * m3 is the first vertex element data we fill, which is the vertex
+ * position.
+ */
+ brw_MOV(p, brw_message_reg(2), pos);
+ brw_MOV(p, brw_message_reg(3), pos);
+ len_vertex_header = 2;
+ } else if (intel->gen == 5) {
+ /* There are 20 DWs (D0-D19) in VUE header on Ironlake:
+ * dword 0-3 (m1) of the header is indices, point width, clip flags.
+ * dword 4-7 (m2) is the ndc position (set above)
+ * dword 8-11 (m3) of the vertex header is the 4D space position
+ * dword 12-19 (m4,m5) of the vertex header is the user clip distance.
+ * m6 is a pad so that the vertex element data is aligned
+ * m7 is the first vertex data we fill, which is the vertex position.
+ */
+ brw_MOV(p, brw_message_reg(2), ndc);
+ brw_MOV(p, brw_message_reg(3), pos);
+ brw_MOV(p, brw_message_reg(7), pos);
+ len_vertex_header = 6;
} else {
- brw_MOV(p, offset(m0, 3), pos);
- len_vertext_header = 2;
+ /* There are 8 dwords in VUE header pre-Ironlake:
+ * dword 0-3 (m1) is indices, point width, clip flags.
+ * dword 4-7 (m2) is ndc position (set above)
+ *
+ * dword 8-11 (m3) is the first vertex data, which we always have be the
+ * vertex position.
+ */
+ brw_MOV(p, brw_message_reg(2), ndc);
+ brw_MOV(p, brw_message_reg(3), pos);
+ len_vertex_header = 2;
}
eot = (c->first_overflow_output == 0);
c->r0, /* src */
0, /* allocate */
1, /* used */
- MIN2(c->nr_outputs + 1 + len_vertext_header, (BRW_MAX_MRF-1)), /* msg len */
+ MIN2(c->nr_outputs + 1 + len_vertex_header, (BRW_MAX_MRF-1)), /* msg len */
0, /* response len */
eot, /* eot */
eot, /* writes complete */
* Move the overflowed attributes from the GRF to the MRF and
* issue another brw_urb_WRITE().
*/
- /* XXX I'm not 100% sure about which MRF regs to use here. Starting
- * at mrf[4] atm...
- */
- GLuint i, mrf = 0;
+ GLuint i, mrf = 1;
for (i = c->first_overflow_output; i < VERT_RESULT_MAX; i++) {
if (c->prog_data.outputs_written & BITFIELD64_BIT(i)) {
/* move from GRF to MRF */
- brw_MOV(p, brw_message_reg(4+mrf), c->regs[PROGRAM_OUTPUT][i]);
+ brw_MOV(p, brw_message_reg(mrf), c->regs[PROGRAM_OUTPUT][i]);
mrf++;
}
}
brw_urb_WRITE(p,
brw_null_reg(), /* dest */
- 4, /* starting mrf reg nr */
+ 0, /* starting mrf reg nr */
c->r0, /* src */
0, /* allocate */
1, /* used */
- mrf+1, /* msg len */
+ mrf, /* msg len */
0, /* response len */
1, /* eot */
1, /* writes complete */
- BRW_MAX_MRF-1, /* urb destination offset */
+ 14 / 2, /* urb destination offset */
BRW_URB_SWIZZLE_INTERLEAVE);
}
}
-
-/**
- * Called after code generation to resolve subroutine calls and the
- * END instruction.
- * \param end_inst points to brw code for END instruction
- * \param last_inst points to last instruction emitted before vertex write
- */
-static void
-post_vs_emit( struct brw_vs_compile *c,
- struct brw_instruction *end_inst,
- struct brw_instruction *last_inst )
-{
- GLint offset;
-
- brw_resolve_cals(&c->func);
-
- /* patch up the END code to jump past subroutines, etc */
- offset = last_inst - end_inst;
- if (offset > 1) {
- brw_set_src1(end_inst, brw_imm_d(offset * 16));
- } else {
- end_inst->header.opcode = BRW_OPCODE_NOP;
- }
-}
-
static GLboolean
accumulator_contains(struct brw_vs_compile *c, struct brw_reg val)
{
struct intel_context *intel = &brw->intel;
const GLuint nr_insns = c->vp->program.Base.NumInstructions;
GLuint insn, if_depth = 0, loop_depth = 0;
- GLuint end_offset = 0;
- struct brw_instruction *end_inst, *last_inst;
- struct brw_instruction *if_inst[MAX_IF_DEPTH], *loop_inst[MAX_LOOP_DEPTH];
+ struct brw_instruction *if_inst[MAX_IF_DEPTH], *loop_inst[MAX_LOOP_DEPTH] = { 0 };
const struct brw_indirect stack_index = brw_indirect(0, 0);
GLuint index;
GLuint file;
if (INTEL_DEBUG & DEBUG_VS) {
- _mesa_printf("vs-mesa:\n");
+ printf("vs-mesa:\n");
_mesa_print_program(&c->vp->program.Base);
- _mesa_printf("\n");
+ printf("\n");
}
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
if_depth++;
break;
case OPCODE_ELSE:
+ assert(if_depth > 0);
if_inst[if_depth-1] = brw_ELSE(p, if_inst[if_depth-1]);
break;
case OPCODE_ENDIF:
loop_depth--;
- if (intel->is_ironlake)
+ if (intel->gen == 5)
br = 2;
inst0 = inst1 = brw_WHILE(p, loop_inst[loop_depth]);
/* patch all the BREAK/CONT instructions from last BEGINLOOP */
while (inst0 > loop_inst[loop_depth]) {
inst0--;
- if (inst0->header.opcode == BRW_OPCODE_BREAK) {
+ if (inst0->header.opcode == BRW_OPCODE_BREAK &&
+ inst0->bits3.if_else.jump_count == 0) {
inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
inst0->bits3.if_else.pop_count = 0;
}
- else if (inst0->header.opcode == BRW_OPCODE_CONTINUE) {
+ else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
+ inst0->bits3.if_else.jump_count == 0) {
inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
inst0->bits3.if_else.pop_count = 0;
}
brw_MOV(p, brw_ip_reg(), deref_1d(stack_index, 0));
brw_set_access_mode(p, BRW_ALIGN_16);
break;
- case OPCODE_END:
- end_offset = p->nr_insn;
- /* this instruction will get patched later to jump past subroutine
- * code, etc.
- */
- brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
+ case OPCODE_END:
+ emit_vertex_write(c);
break;
case OPCODE_PRINT:
/* no-op */
release_tmps(c);
}
- end_inst = &p->store[end_offset];
- last_inst = &p->store[p->nr_insn];
-
- /* The END instruction will be patched to jump to this code */
- emit_vertex_write(c);
+ brw_resolve_cals(p);
- post_vs_emit(c, end_inst, last_inst);
+ brw_optimize(p);
if (INTEL_DEBUG & DEBUG_VS) {
int i;
- _mesa_printf("vs-native:\n");
+ printf("vs-native:\n");
for (i = 0; i < p->nr_insn; i++)
- brw_disasm(stderr, &p->store[i]);
- _mesa_printf("\n");
+ brw_disasm(stderr, &p->store[i], intel->gen);
+ printf("\n");
}
}
projects / mesa.git / blobdiff