*/
vs.thread1.single_program_flow = 0;
- if (intel->is_ironlake)
+ if (intel->gen == 5)
vs.thread1.binding_table_entry_count = 0; /* hardware requirement */
else
vs.thread1.binding_table_entry_count = key->nr_surfaces;
vs.thread3.urb_entry_read_offset = 0;
vs.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
- if (intel->is_ironlake) {
+ if (intel->gen == 5) {
switch (key->nr_urb_entries) {
case 8:
case 12:
/* No samplers for ARB_vp programs:
*/
- /* It has to be set to 0 for IGDNG
+ /* It has to be set to 0 for Ironlake
*/
vs.vs5.sampler_count = 0;
bo = brw_upload_cache(&brw->cache, BRW_VS_UNIT,
key, sizeof(*key),
&brw->vs.prog_bo, 1,
- &vs, sizeof(vs),
- NULL, NULL);
+ &vs, sizeof(vs));
/* Emit VS program relocation */
dri_bo_emit_reloc(bo,