intel: Add a batch flush between front-buffer downsample and X protocol.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vs_state.c

diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
index 54ff754b1ddc4b4126da7d18f2ccef759204d88f..e5421f1c3a9e11115624bbe07c1775a02ee6aec7 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -55,7 +55,14 @@ brw_upload_vs_unit(struct brw_context *brw)
                        brw->vs.prog_offset +
                        (vs->thread0.grf_reg_count << 1)) >> 6;
 
-   vs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
+   /* Use ALT floating point mode for ARB vertex programs, because they
+    * require 0^0 == 1.
+    */
+   if (brw->ctx.Shader.CurrentVertexProgram == NULL)
+      vs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
+   else
+      vs->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754;
+
    /* Choosing multiple program flow means that we may get 2-vertex threads,
     * which will have the channel mask for dwords 4-7 enabled in the thread,
     * and those dwords will be written to the second URB handle when we
@@ -85,7 +92,8 @@ brw_upload_vs_unit(struct brw_context *brw)
    vs->thread3.urb_entry_read_length = brw->vs.prog_data->base.urb_read_length;
    vs->thread3.const_urb_entry_read_length
       = brw->vs.prog_data->base.curb_read_length;
-   vs->thread3.dispatch_grf_start_reg = 1;
+   vs->thread3.dispatch_grf_start_reg =
+      brw->vs.prog_data->base.dispatch_grf_start_reg;
    vs->thread3.urb_entry_read_offset = 0;
 
    /* BRW_NEW_CURBE_OFFSETS, _NEW_TRANSFORM, BRW_NEW_VERTEX_PROGRAM */
@@ -131,11 +139,13 @@ brw_upload_vs_unit(struct brw_context *brw)
    vs->thread4.max_threads = CLAMP(brw->urb.nr_vs_entries / 2,
                                   1, brw->max_vs_threads) - 1;
 
-   /* No samplers for ARB_vp programs:
-    */
-   /* It has to be set to 0 for Ironlake
-    */
-   vs->vs5.sampler_count = 0;
+   if (brw->gen == 5)
+      vs->vs5.sampler_count = 0; /* hardware requirement */
+   else {
+      /* CACHE_NEW_SAMPLER */
+      vs->vs5.sampler_count = (brw->vs.sampler_count + 3) / 4;
+   }
+
 
    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
       vs->thread4.stats_enable = 1;
@@ -144,6 +154,19 @@ brw_upload_vs_unit(struct brw_context *brw)
     */
    vs->vs6.vs_enable = 1;
 
+   /* Set the sampler state pointer, and its reloc
+    */
+   if (brw->vs.sampler_count) {
+      vs->vs5.sampler_state_pointer =
+         (brw->batch.bo->offset + brw->vs.sampler_offset) >> 5;
+      drm_intel_bo_emit_reloc(brw->batch.bo,
+                              brw->vs.state_offset +
+                              offsetof(struct brw_vs_unit_state, vs5),
+                              brw->batch.bo,
+                              brw->vs.sampler_offset | vs->vs5.sampler_count,
+                              I915_GEM_DOMAIN_INSTRUCTION, 0);
+   }
+
    /* Emit scratch space relocation */
    if (brw->vs.prog_data->base.total_scratch != 0) {
       drm_intel_bo_emit_reloc(brw->batch.bo,
@@ -165,7 +188,7 @@ const struct brw_tracked_state brw_vs_unit = {
                BRW_NEW_CURBE_OFFSETS |
                BRW_NEW_URB_FENCE |
                 BRW_NEW_VERTEX_PROGRAM),
-      .cache = CACHE_NEW_VS_PROG
+      .cache = CACHE_NEW_VS_PROG | CACHE_NEW_SAMPLER
    },
    .emit = brw_upload_vs_unit,
 };