i965: Use state streaming on programs, and state base address on gen5+.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vtbl.c

diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 28d5f62f34bcb75c9f0f3d8e7e7bf81760927331..0f731482629a6783d63bc8e5513bcfc1c13d5cdd 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -68,17 +68,9 @@ static void brw_destroy_context( struct intel_context *intel )
    brw_clear_validated_bos(brw);
    ralloc_free(brw->wm.compile_data);
 
-   intel_region_release(&brw->state.depth_region);
-
    dri_bo_release(&brw->curbe.curbe_bo);
-   dri_bo_release(&brw->vs.prog_bo);
    dri_bo_release(&brw->vs.const_bo);
-   dri_bo_release(&brw->gs.prog_bo);
-   dri_bo_release(&brw->clip.prog_bo);
-   dri_bo_release(&brw->sf.prog_bo);
-   dri_bo_release(&brw->wm.prog_bo);
    dri_bo_release(&brw->wm.const_bo);
-   dri_bo_release(&brw->cc.prog_bo);
 
    free(brw->curbe.last_buf);
    free(brw->curbe.next_buf);
@@ -93,13 +85,6 @@ static void brw_set_draw_region( struct intel_context *intel,
                                  struct intel_region *depth_region,
                                  GLuint num_color_regions)
 {
-   struct brw_context *brw = brw_context(&intel->ctx);
-
-   if (brw->state.depth_region != depth_region) {
-      brw->state.dirty.brw |= BRW_NEW_DEPTH_BUFFER;
-      intel_region_release(&brw->state.depth_region);
-      intel_region_reference(&brw->state.depth_region, depth_region);
-   }
 }
 
 
@@ -131,13 +116,15 @@ static void brw_new_batch( struct intel_context *intel )
     * This is probably not as severe as on 915, since almost all of our state
     * is just in referenced buffers.
     */
-   brw->state.dirty.brw |= BRW_NEW_CONTEXT;
-
-   brw->state.dirty.mesa |= ~0;
-   brw->state.dirty.brw |= ~0;
-   brw->state.dirty.cache |= ~0;
+   brw->state.dirty.brw |= BRW_NEW_CONTEXT | BRW_NEW_BATCH;
 
    brw->vb.nr_current_buffers = 0;
+
+   /* Mark that the current program cache BO has been used by the GPU.
+    * It will be reallocated if we need to put new programs in for the
+    * next batch.
+    */
+   brw->cache.bo_used_by_gpu = true;
 }
 
 static void brw_invalidate_state( struct intel_context *intel, GLuint new_state )
@@ -145,6 +132,16 @@ static void brw_invalidate_state( struct intel_context *intel, GLuint new_state
    /* nothing */
 }
 
+/**
+ * \see intel_context.vtbl.is_hiz_depth_format
+ */
+static bool brw_is_hiz_depth_format(struct intel_context *intel,
+                                    gl_format format)
+{
+   /* In the future, this will support Z_FLOAT32. */
+   return intel->has_hiz && (format == MESA_FORMAT_X8_Z24);
+}
+
 
 void brwInitVtbl( struct brw_context *brw )
 {
@@ -161,4 +158,5 @@ void brwInitVtbl( struct brw_context *brw )
    brw->intel.vtbl.set_draw_region = brw_set_draw_region;
    brw->intel.vtbl.debug_batch = brw_debug_batch;
    brw->intel.vtbl.render_target_supported = brw_render_target_supported;
+   brw->intel.vtbl.is_hiz_depth_format = brw_is_hiz_depth_format;
 }