i965: Use state streaming on programs, and state base address on gen5+.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vtbl.c

diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 681319dedfdf1273d3d20f7fbd30822bcb0ff433..0f731482629a6783d63bc8e5513bcfc1c13d5cdd 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -43,14 +43,15 @@
 #include "brw_defines.h"
 #include "brw_state.h"
 #include "brw_draw.h"
-#include "brw_state.h"
 #include "brw_vs.h"
 #include "brw_wm.h"
 
+#include "../glsl/ralloc.h"
+
 static void
-dri_bo_release(dri_bo **bo)
+dri_bo_release(drm_intel_bo **bo)
 {
-   dri_bo_unreference(*bo);
+   drm_intel_bo_unreference(*bo);
    *bo = NULL;
 }
 
@@ -61,47 +62,18 @@ dri_bo_release(dri_bo **bo)
 static void brw_destroy_context( struct intel_context *intel )
 {
    struct brw_context *brw = brw_context(&intel->ctx);
-   int i;
 
    brw_destroy_state(brw);
    brw_draw_destroy( brw );
    brw_clear_validated_bos(brw);
-   if (brw->wm.compile_data) {
-      _mesa_free(brw->wm.compile_data->instruction);
-      _mesa_free(brw->wm.compile_data->vreg);
-      _mesa_free(brw->wm.compile_data->refs);
-      _mesa_free(brw->wm.compile_data->prog_instructions);
-      _mesa_free(brw->wm.compile_data);
-   }
-
-   for (i = 0; i < brw->state.nr_color_regions; i++)
-      intel_region_release(&brw->state.color_regions[i]);
-   brw->state.nr_color_regions = 0;
-   intel_region_release(&brw->state.depth_region);
+   ralloc_free(brw->wm.compile_data);
 
    dri_bo_release(&brw->curbe.curbe_bo);
-   dri_bo_release(&brw->vs.prog_bo);
-   dri_bo_release(&brw->vs.state_bo);
-   dri_bo_release(&brw->vs.bind_bo);
-   dri_bo_release(&brw->gs.prog_bo);
-   dri_bo_release(&brw->gs.state_bo);
-   dri_bo_release(&brw->clip.prog_bo);
-   dri_bo_release(&brw->clip.state_bo);
-   dri_bo_release(&brw->clip.vp_bo);
-   dri_bo_release(&brw->sf.prog_bo);
-   dri_bo_release(&brw->sf.state_bo);
-   dri_bo_release(&brw->sf.vp_bo);
-   for (i = 0; i < BRW_MAX_TEX_UNIT; i++)
-      dri_bo_release(&brw->wm.sdc_bo[i]);
-   dri_bo_release(&brw->wm.bind_bo);
-   for (i = 0; i < BRW_WM_MAX_SURF; i++)
-      dri_bo_release(&brw->wm.surf_bo[i]);
-   dri_bo_release(&brw->wm.sampler_bo);
-   dri_bo_release(&brw->wm.prog_bo);
-   dri_bo_release(&brw->wm.state_bo);
-   dri_bo_release(&brw->cc.prog_bo);
-   dri_bo_release(&brw->cc.state_bo);
-   dri_bo_release(&brw->cc.vp_bo);
+   dri_bo_release(&brw->vs.const_bo);
+   dri_bo_release(&brw->wm.const_bo);
+
+   free(brw->curbe.last_buf);
+   free(brw->curbe.next_buf);
 }
 
 
@@ -113,21 +85,6 @@ static void brw_set_draw_region( struct intel_context *intel,
                                  struct intel_region *depth_region,
                                  GLuint num_color_regions)
 {
-   struct brw_context *brw = brw_context(&intel->ctx);
-   GLuint i;
-
-   /* release old color/depth regions */
-   if (brw->state.depth_region != depth_region)
-      brw->state.dirty.brw |= BRW_NEW_DEPTH_BUFFER;
-   for (i = 0; i < brw->state.nr_color_regions; i++)
-       intel_region_release(&brw->state.color_regions[i]);
-   intel_region_release(&brw->state.depth_region);
-
-   /* reference new color/depth regions */
-   for (i = 0; i < num_color_regions; i++)
-       intel_region_reference(&brw->state.color_regions[i], color_regions[i]);
-   intel_region_reference(&brw->state.depth_region, depth_region);
-   brw->state.nr_color_regions = num_color_regions;
 }
 
 
@@ -141,7 +98,7 @@ static void brw_finish_batch(struct intel_context *intel)
    brw_emit_query_end(brw);
 
    if (brw->curbe.curbe_bo) {
-      intel_bo_unmap_gtt_preferred(intel, brw->curbe.curbe_bo);
+      drm_intel_gem_bo_unmap_gtt(brw->curbe.curbe_bo);
       drm_intel_bo_unreference(brw->curbe.curbe_bo);
       brw->curbe.curbe_bo = NULL;
    }
@@ -159,20 +116,15 @@ static void brw_new_batch( struct intel_context *intel )
     * This is probably not as severe as on 915, since almost all of our state
     * is just in referenced buffers.
     */
-   brw->state.dirty.brw |= BRW_NEW_CONTEXT;
+   brw->state.dirty.brw |= BRW_NEW_CONTEXT | BRW_NEW_BATCH;
 
-   brw->state.dirty.mesa |= ~0;
-   brw->state.dirty.brw |= ~0;
-   brw->state.dirty.cache |= ~0;
+   brw->vb.nr_current_buffers = 0;
 
-   /* Move to the end of the current upload buffer so that we'll force choosing
-    * a new buffer next time.
+   /* Mark that the current program cache BO has been used by the GPU.
+    * It will be reallocated if we need to put new programs in for the
+    * next batch.
     */
-   if (brw->vb.upload.bo != NULL) {
-      dri_bo_unreference(brw->vb.upload.bo);
-      brw->vb.upload.bo = NULL;
-      brw->vb.upload.offset = 0;
-   }
+   brw->cache.bo_used_by_gpu = true;
 }
 
 static void brw_invalidate_state( struct intel_context *intel, GLuint new_state )
@@ -180,6 +132,16 @@ static void brw_invalidate_state( struct intel_context *intel, GLuint new_state
    /* nothing */
 }
 
+/**
+ * \see intel_context.vtbl.is_hiz_depth_format
+ */
+static bool brw_is_hiz_depth_format(struct intel_context *intel,
+                                    gl_format format)
+{
+   /* In the future, this will support Z_FLOAT32. */
+   return intel->has_hiz && (format == MESA_FORMAT_X8_Z24);
+}
+
 
 void brwInitVtbl( struct brw_context *brw )
 {
@@ -195,4 +157,6 @@ void brwInitVtbl( struct brw_context *brw )
    brw->intel.vtbl.destroy = brw_destroy_context;
    brw->intel.vtbl.set_draw_region = brw_set_draw_region;
    brw->intel.vtbl.debug_batch = brw_debug_batch;
+   brw->intel.vtbl.render_target_supported = brw_render_target_supported;
+   brw->intel.vtbl.is_hiz_depth_format = brw_is_hiz_depth_format;
 }