i965/gs: Add a case to brwNewProgram() for geometry shaders.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_vtbl.c

diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index d19ca0be5136016b48f7aff50f2f2d6edb0376bd..aee88e0ea4f4a9bae524a2f0e9a923b905c79efb 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -117,8 +117,6 @@ brw_finish_batch(struct brw_context *brw)
 static void
 brw_new_batch(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-
    /* If the kernel supports hardware contexts, then most hardware state is
     * preserved between batches; we only need to re-emit state that is required
     * to be in every batch.  Otherwise we need to re-emit all the state that
@@ -133,7 +131,7 @@ brw_new_batch(struct brw_context *brw)
    /* Assume that the last command before the start of our batch was a
     * primitive, for safety.
     */
-   intel->batch.need_workaround_flush = true;
+   brw->batch.need_workaround_flush = true;
 
    brw->state_batch_count = 0;
 
@@ -160,12 +158,14 @@ void brwInitVtbl( struct brw_context *brw )
    brw->vtbl.finish_batch = brw_finish_batch;
    brw->vtbl.destroy = brw_destroy_context;
 
-   assert(brw->intel.gen >= 4);
-   if (brw->intel.gen >= 7) {
+   assert(brw->gen >= 4);
+   if (brw->gen >= 7) {
       gen7_init_vtable_surface_functions(brw);
+      gen7_init_vtable_sampler_functions(brw);
       brw->vtbl.emit_depth_stencil_hiz = gen7_emit_depth_stencil_hiz;
-   } else if (brw->intel.gen >= 4) {
+   } else if (brw->gen >= 4) {
       gen4_init_vtable_surface_functions(brw);
+      gen4_init_vtable_sampler_functions(brw);
       brw->vtbl.emit_depth_stencil_hiz = brw_emit_depth_stencil_hiz;
    }
 }