{
struct gl_context *ctx = &intel->ctx;
struct gl_framebuffer *fb = ctx->DrawBuffer;
- struct intel_renderbuffer *irbStencil = NULL;
- bool fb_has_hiz = intel_framebuffer_has_hiz(fb);
if (!fb) {
/* this can happen during the initial context initialization */
return;
}
- irbStencil = intel_get_renderbuffer(fb, BUFFER_STENCIL);
-
/* Do this here, not core Mesa, since this function is called from
* many places within the driver.
*/
return;
}
- /* Check some stencil invariants. These should probably be in
- * emit_depthbuffer().
- */
- if (irbStencil && irbStencil->mt) {
- if (!intel->has_separate_stencil)
- assert(irbStencil->Base.Format == MESA_FORMAT_S8_Z24);
- if (fb_has_hiz || intel->must_use_separate_stencil)
- assert(irbStencil->Base.Format == MESA_FORMAT_S8);
- if (irbStencil->Base.Format == MESA_FORMAT_S8)
- assert(intel->has_separate_stencil);
- }
-
/* Mesa's Stencil._Enabled field is updated when
* _NEW_BUFFERS | _NEW_STENCIL, but i965 code assumes that the value
* only changes with _NEW_STENCIL (which seems sensible). So flag it
brw->state_batch_count = 0;
+ /* Gen7 needs to track what the real transform feedback vertex count was at
+ * the start of the batch, since the kernel will be resetting the offset to
+ * 0.
+ */
+ brw->sol.offset_0_batch_start = brw->sol.svbi_0_starting_index;
+
brw->vb.nr_current_buffers = 0;
brw->ib.type = -1;
static bool brw_is_hiz_depth_format(struct intel_context *intel,
gl_format format)
{
- /* In the future, this will support Z_FLOAT32. */
- return intel->has_hiz && (format == MESA_FORMAT_X8_Z24);
+ if (!intel->has_hiz)
+ return false;
+
+ switch (format) {
+ case MESA_FORMAT_Z32_FLOAT:
+ case MESA_FORMAT_Z32_FLOAT_X24S8:
+ case MESA_FORMAT_X8_Z24:
+ case MESA_FORMAT_S8_Z24:
+ return true;
+ default:
+ return false;
+ }
}
void brwInitVtbl( struct brw_context *brw )
brw->intel.vtbl.is_hiz_depth_format = brw_is_hiz_depth_format;
if (brw->intel.has_hiz) {
- brw->intel.vtbl.hiz_resolve_hizbuffer = gen6_hiz_resolve_hizbuffer;
- brw->intel.vtbl.hiz_resolve_depthbuffer = gen6_hiz_resolve_depthbuffer;
+ brw->intel.vtbl.resolve_depth_slice = gen6_resolve_depth_slice;
+ brw->intel.vtbl.resolve_hiz_slice = gen6_resolve_hiz_slice;
}
if (brw->intel.gen >= 7) {