Merge branch 'mesa_7_5_branch'

[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm.c

diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index 879000644b21d6f34d72aca8e54651f54e8f456d..34c8ceddb72b590b9eb5aad61bb8768e49044152 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -40,6 +40,8 @@
 GLuint brw_wm_nr_args( GLuint opcode )
 {
    switch (opcode) {
+   case WM_FRONTFACING:
+      return 0;
    case WM_PIXELXY:
    case WM_CINTERP:
    case WM_WPOSXY:
@@ -103,12 +105,17 @@ brw_wm_non_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c)
    brw_wm_pass1(c);
 
    /* Register allocation.
+    * Divide by two because we operate on 16 pixels at a time and require
+    * two GRF entries for each logical shader register.
     */
    c->grf_limit = BRW_WM_MAX_GRF / 2;
 
    brw_wm_pass2(c);
 
+   /* how many general-purpose registers are used */
    c->prog_data.total_grf = c->max_wm_grf;
+
+   /* Scratch space is used for register spilling */
    if (c->last_scratch) {
       c->prog_data.total_scratch = c->last_scratch + 0x40;
    }
@@ -139,6 +146,13 @@ static void do_wm_prog( struct brw_context *brw,
    if (c == NULL) {
       brw->wm.compile_data = calloc(1, sizeof(*brw->wm.compile_data));
       c = brw->wm.compile_data;
+      if (c == NULL) {
+         /* Ouch - big out of memory problem.  Can't continue
+          * without triggering a segfault, no way to signal,
+          * so just return.
+          */
+         return;
+      }
    } else {
       memset(c, 0, sizeof(*brw->wm.compile_data));
    }
@@ -149,11 +163,14 @@ static void do_wm_prog( struct brw_context *brw,
 
    brw_init_compile(brw, &c->func);
 
+   /* temporary sanity check assertion */
+   ASSERT(fp->isGLSL == brw_wm_is_glsl(&c->fp->program));
+
    /*
     * Shader which use GLSL features such as flow control are handled
     * differently from "simple" shaders.
     */
-   if (brw_wm_is_glsl(&c->fp->program)) {
+   if (fp->isGLSL) {
       brw_wm_glsl_emit(brw, c);
    }
    else {
@@ -255,6 +272,9 @@ static void brw_wm_populate_key( struct brw_context *brw,
    /* _NEW_LIGHT */
    key->flat_shade = (ctx->Light.ShadeModel == GL_FLAT);
 
+   /* _NEW_HINT */
+   key->linear_color = (ctx->Hint.PerspectiveCorrection == GL_FASTEST);
+
    /* _NEW_TEXTURE */
    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
       const struct gl_texture_unit *unit = &ctx->Texture.Unit[i];
@@ -302,6 +322,9 @@ static void brw_wm_populate_key( struct brw_context *brw,
       key->drawable_height = brw->intel.driDrawable->h;
    }
 
+   /* CACHE_NEW_VS_PROG */
+   key->vp_outputs_written = brw->vs.prog_data->outputs_written & DO_SETUP_BITS;
+
    /* The unique fragment program ID */
    key->program_string_id = fp->id;
 }
@@ -331,6 +354,7 @@ const struct brw_tracked_state brw_wm_prog = {
    .dirty = {
       .mesa  = (_NEW_COLOR |
                _NEW_DEPTH |
+                _NEW_HINT |
                _NEW_STENCIL |
                _NEW_POLYGON |
                _NEW_LINE |
@@ -340,7 +364,7 @@ const struct brw_tracked_state brw_wm_prog = {
       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
                BRW_NEW_WM_INPUT_DIMENSIONS |
                BRW_NEW_REDUCED_PRIMITIVE),
-      .cache = 0
+      .cache = CACHE_NEW_VS_PROG,
    },
    .prepare = brw_prepare_wm_prog
 };