#include "program/program.h"
#include "intel_mipmap_tree.h"
#include "intel_image.h"
+#include "intel_fbo.h"
#include "compiler/brw_nir.h"
#include "brw_program.h"
#include "util/ralloc.h"
+#include "util/u_math.h"
static void
assign_fs_binding_table_offsets(const struct gen_device_info *devinfo,
const struct brw_wm_prog_key *key,
struct brw_wm_prog_data *prog_data)
{
- uint32_t next_binding_table_offset = 0;
-
- /* If there are no color regions, we still perform an FB write to a null
- * renderbuffer, which we place at surface index 0.
+ /* Render targets implicitly start at surface index 0. Even if there are
+ * no color regions, we still perform an FB write to a null render target,
+ * which will be surface 0.
*/
- prog_data->binding_table.render_target_start = next_binding_table_offset;
- next_binding_table_offset += MAX2(key->nr_color_regions, 1);
+ uint32_t next_binding_table_offset = MAX2(key->nr_color_regions, 1);
next_binding_table_offset =
brw_assign_common_binding_table_offsets(devinfo, prog, &prog_data->base,
next_binding_table_offset;
next_binding_table_offset += key->nr_color_regions;
}
+
+ /* Update the binding table size */
+ prog_data->base.binding_table.size_bytes = next_binding_table_offset * 4;
}
static void
bool start_busy = false;
double start_time = 0;
+ nir_shader *nir = nir_shader_clone(mem_ctx, fp->program.nir);
+
memset(&prog_data, 0, sizeof(prog_data));
/* Use ALT floating point mode for ARB programs so that 0^0 == 1. */
assign_fs_binding_table_offsets(devinfo, &fp->program, key, &prog_data);
if (!fp->program.is_arb_asm) {
- brw_nir_setup_glsl_uniforms(mem_ctx, fp->program.nir, &fp->program,
+ brw_nir_setup_glsl_uniforms(mem_ctx, nir, &fp->program,
&prog_data.base, true);
- brw_nir_analyze_ubo_ranges(brw->screen->compiler, fp->program.nir,
- prog_data.base.ubo_ranges);
+ brw_nir_analyze_ubo_ranges(brw->screen->compiler, nir,
+ NULL, prog_data.base.ubo_ranges);
} else {
- brw_nir_setup_arb_uniforms(mem_ctx, fp->program.nir, &fp->program,
- &prog_data.base);
+ brw_nir_setup_arb_uniforms(mem_ctx, nir, &fp->program, &prog_data.base);
if (unlikely(INTEL_DEBUG & DEBUG_WM))
brw_dump_arb_asm("fragment", &fp->program);
start_time = get_time();
}
- int st_index8 = -1, st_index16 = -1;
+ int st_index8 = -1, st_index16 = -1, st_index32 = -1;
if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
st_index8 = brw_get_shader_time_index(brw, &fp->program, ST_FS8,
!fp->program.is_arb_asm);
st_index16 = brw_get_shader_time_index(brw, &fp->program, ST_FS16,
!fp->program.is_arb_asm);
+ st_index32 = brw_get_shader_time_index(brw, &fp->program, ST_FS32,
+ !fp->program.is_arb_asm);
}
char *error_str = NULL;
program = brw_compile_fs(brw->screen->compiler, brw, mem_ctx,
- key, &prog_data, fp->program.nir,
- &fp->program, st_index8, st_index16,
+ key, &prog_data, nir,
+ &fp->program, st_index8, st_index16, st_index32,
true, false, vue_map,
&error_str);
if (program == NULL) {
if (!fp->program.is_arb_asm) {
- fp->program.sh.data->LinkStatus = linking_failure;
+ fp->program.sh.data->LinkStatus = LINKING_FAILURE;
ralloc_strcat(&fp->program.sh.data->InfoLog, error_str);
}
found |= key_debug(brw, "xy_uxvx image bound",
old_key->xy_uxvx_image_mask,
key->xy_uxvx_image_mask);
-
+ found |= key_debug(brw, "ayuv image bound",
+ old_key->ayuv_image_mask,
+ key->ayuv_image_mask);
+ found |= key_debug(brw, "xyuv image bound",
+ old_key->xyuv_image_mask,
+ key->xyuv_image_mask);
for (unsigned int i = 0; i < MAX_SAMPLERS; i++) {
found |= key_debug(brw, "textureGather workarounds",
old_key->gen6_gather_wa[i], key->gen6_gather_wa[i]);
}
+ for (unsigned int i = 0; i < MAX_SAMPLERS; i++) {
+ found |= key_debug_float(brw, "scale factor",
+ old_key->scale_factors[i],
+ key->scale_factors[i]);
+ }
+
return found;
}
const int s = u_bit_scan(&mask);
key->swizzles[s] = SWIZZLE_NOOP;
+ key->scale_factors[s] = 0.0f;
int unit_id = prog->SamplerUnits[s];
const struct gl_texture_unit *unit = &ctx->Texture.Unit[unit_id];
if (intel_tex->mt->aux_usage == ISL_AUX_USAGE_MCS) {
assert(devinfo->gen >= 7);
assert(intel_tex->mt->surf.samples > 1);
- assert(intel_tex->mt->mcs_buf);
+ assert(intel_tex->mt->aux_buf);
assert(intel_tex->mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
key->compressed_multisample_layout_mask |= 1 << s;
}
if (t->Target == GL_TEXTURE_EXTERNAL_OES && intel_tex->planar_format) {
+
+ /* Setup possible scaling factor. */
+ key->scale_factors[s] = intel_tex->planar_format->scaling_factor;
+
switch (intel_tex->planar_format->components) {
case __DRI_IMAGE_COMPONENTS_Y_UV:
key->y_uv_image_mask |= 1 << s;
case __DRI_IMAGE_COMPONENTS_Y_UXVX:
key->xy_uxvx_image_mask |= 1 << s;
break;
+ case __DRI_IMAGE_COMPONENTS_AYUV:
+ key->ayuv_image_mask |= 1 << s;
+ break;
+ case __DRI_IMAGE_COMPONENTS_XYUV:
+ key->xyuv_image_mask |= 1 << s;
+ break;
default:
break;
}
/* Build the index for table lookup
*/
if (devinfo->gen < 6) {
+ struct intel_renderbuffer *depth_irb =
+ intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
+
/* _NEW_COLOR */
if (prog->info.fs.uses_discard || ctx->Color.AlphaEnabled) {
lookup |= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT;
}
/* _NEW_DEPTH */
- if (ctx->Depth.Test)
+ if (depth_irb && ctx->Depth.Test) {
lookup |= BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT;
- if (brw_depth_writes_enabled(brw))
- lookup |= BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT;
+ if (brw_depth_writes_enabled(brw))
+ lookup |= BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT;
+ }
/* _NEW_STENCIL | _NEW_BUFFERS */
if (brw->stencil_enabled) {
}
/* BRW_NEW_VUE_MAP_GEOM_OUT */
- if (devinfo->gen < 6 || _mesa_bitcount_64(prog->info.inputs_read &
+ if (devinfo->gen < 6 || util_bitcount64(prog->info.inputs_read &
BRW_FS_VARYING_INPUT_MASK) > 16) {
key->input_slots_valid = brw->vue_map_geom_out.slots_valid;
}
key->program_string_id = fp->id;
/* Whether reads from the framebuffer should behave coherently. */
- key->coherent_fb_fetch = ctx->Extensions.MESA_shader_framebuffer_fetch;
+ key->coherent_fb_fetch = ctx->Extensions.EXT_shader_framebuffer_fetch;
}
void
brw_wm_populate_key(brw, &key);
- if (brw_search_cache(&brw->cache, BRW_CACHE_FS_PROG,
- &key, sizeof(key),
- &brw->wm.base.prog_offset,
- &brw->wm.base.prog_data))
+ if (brw_search_cache(&brw->cache, BRW_CACHE_FS_PROG, &key, sizeof(key),
+ &brw->wm.base.prog_offset, &brw->wm.base.prog_data,
+ true))
return;
if (brw_disk_cache_upload_program(brw, MESA_SHADER_FRAGMENT))
assert(success);
}
-bool
-brw_fs_precompile(struct gl_context *ctx, struct gl_program *prog)
+void
+brw_wm_populate_default_key(const struct gen_device_info *devinfo,
+ struct brw_wm_prog_key *key,
+ struct gl_program *prog)
{
- struct brw_context *brw = brw_context(ctx);
- const struct gen_device_info *devinfo = &brw->screen->devinfo;
- struct brw_wm_prog_key key;
-
- struct brw_program *bfp = brw_program(prog);
-
- memset(&key, 0, sizeof(key));
+ memset(key, 0, sizeof(*key));
uint64_t outputs_written = prog->info.outputs_written;
if (devinfo->gen < 6) {
if (prog->info.fs.uses_discard)
- key.iz_lookup |= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT;
+ key->iz_lookup |= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT;
if (outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
- key.iz_lookup |= BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT;
+ key->iz_lookup |= BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT;
/* Just assume depth testing. */
- key.iz_lookup |= BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT;
- key.iz_lookup |= BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT;
+ key->iz_lookup |= BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT;
+ key->iz_lookup |= BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT;
}
- if (devinfo->gen < 6 || _mesa_bitcount_64(prog->info.inputs_read &
+ if (devinfo->gen < 6 || util_bitcount64(prog->info.inputs_read &
BRW_FS_VARYING_INPUT_MASK) > 16) {
- key.input_slots_valid = prog->info.inputs_read | VARYING_BIT_POS;
+ key->input_slots_valid = prog->info.inputs_read | VARYING_BIT_POS;
}
- brw_setup_tex_for_precompile(brw, &key.tex, prog);
+ brw_setup_tex_for_precompile(devinfo, &key->tex, prog);
- key.nr_color_regions = _mesa_bitcount_64(outputs_written &
+ key->nr_color_regions = util_bitcount64(outputs_written &
~(BITFIELD64_BIT(FRAG_RESULT_DEPTH) |
BITFIELD64_BIT(FRAG_RESULT_STENCIL) |
BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK)));
- key.program_string_id = bfp->id;
+ key->program_string_id = brw_program(prog)->id;
/* Whether reads from the framebuffer should behave coherently. */
- key.coherent_fb_fetch = ctx->Extensions.MESA_shader_framebuffer_fetch;
+ key->coherent_fb_fetch = devinfo->gen >= 9;
+}
+
+bool
+brw_fs_precompile(struct gl_context *ctx, struct gl_program *prog)
+{
+ struct brw_context *brw = brw_context(ctx);
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+ struct brw_wm_prog_key key;
+
+ struct brw_program *bfp = brw_program(prog);
+
+ brw_wm_populate_default_key(&brw->screen->devinfo, &key, prog);
+
+ /* check brw_wm_populate_default_key coherent_fb_fetch setting */
+ assert(key.coherent_fb_fetch ==
+ ctx->Extensions.EXT_shader_framebuffer_fetch);
uint32_t old_prog_offset = brw->wm.base.prog_offset;
struct brw_stage_prog_data *old_prog_data = brw->wm.base.prog_data;