i965: Add HiZ operation state to brw_context

[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm.h

diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h
index e244b55a083d6a565e2c802b9f4b1067a17451ee..056934a274b4937e7f4cd723d4821b9017ed9be7 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -68,6 +68,18 @@ struct brw_wm_prog_key {
    GLuint clamp_fragment_color:1;
    GLuint line_aa:2;
 
+   /**
+    * Per-sampler comparison functions:
+    *
+    * If comparison mode is GL_COMPARE_R_TO_TEXTURE, then this is set to one
+    * of GL_NEVER, GL_LESS, GL_EQUAL, GL_LEQUAL, GL_GREATER, GL_NOTEQUAL,
+    * GL_GEQUAL, or GL_ALWAYS.  Otherwise (comparison mode is GL_NONE), this
+    * field is irrelevant so it's left as GL_NONE (0).
+    *
+    * While this is a GLenum, all possible values fit in 16-bits.
+    */
+   uint16_t compare_funcs[BRW_MAX_TEX_UNIT];
+
    GLbitfield proj_attrib_mask; /**< one bit per fragment program attribute */
    GLuint yuvtex_mask:16;
    GLuint yuvtex_swap_mask:16; /* UV swaped */
@@ -144,7 +156,7 @@ struct brw_wm_instruction {
    GLuint saturate:1;
    GLuint writemask:4;
    GLuint tex_unit:4;   /* texture unit for TEX, TXD, TXP instructions */
-   GLuint tex_idx:3;    /* TEXTURE_1D,2D,3D,CUBE,RECT_INDEX source target */
+   GLuint tex_idx:4;    /* TEXTURE_1D,2D,3D,CUBE,RECT_INDEX source target */
    GLuint tex_shadow:1; /* do shadow comparison? */
    GLuint eot:1;       /* End of thread indicator for FB_WRITE*/
    GLuint target:10;    /* target binding table index for FB_WRITE*/
@@ -203,6 +215,7 @@ struct brw_wm_compile {
    uint8_t source_w_reg;
    uint8_t aa_dest_stencil_reg;
    uint8_t dest_depth_reg;
+   uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
    uint8_t nr_payload_regs;
    GLuint computes_depth:1;    /* could be derived from program string */
    GLuint source_depth_to_render_target:1;
@@ -256,15 +269,15 @@ struct brw_wm_compile {
 
    GLuint cur_inst;  /**< index of current instruction */
 
-   GLboolean out_of_regs;  /**< ran out of GRF registers? */
+   bool out_of_regs;  /**< ran out of GRF registers? */
 
    /** Mapping from Mesa registers to hardware registers */
    struct {
-      GLboolean inited;
+      bool inited;
       struct brw_reg reg;
    } wm_regs[NUM_FILES][256][4];
 
-   GLboolean used_grf[BRW_WM_MAX_GRF];
+   bool used_grf[BRW_WM_MAX_GRF];
    GLuint first_free_grf;
    struct brw_reg stack;
    struct brw_reg emit_mask_reg;
@@ -296,7 +309,7 @@ void brw_wm_pass0( struct brw_wm_compile *c );
 void brw_wm_pass1( struct brw_wm_compile *c );
 void brw_wm_pass2( struct brw_wm_compile *c );
 void brw_wm_emit( struct brw_wm_compile *c );
-GLboolean brw_wm_arg_can_be_immediate(enum prog_opcode, int arg);
+bool brw_wm_arg_can_be_immediate(enum prog_opcode, int arg);
 void brw_wm_print_value( struct brw_wm_compile *c,
                         struct brw_wm_value *value );
 
@@ -345,7 +358,7 @@ void emit_cmp(struct brw_compile *p,
 void emit_ddxy(struct brw_compile *p,
               const struct brw_reg *dst,
               GLuint mask,
-              GLboolean is_ddx,
+              bool is_ddx,
               const struct brw_reg *arg0);
 void emit_delta_xy(struct brw_compile *p,
                   const struct brw_reg *dst,
@@ -449,7 +462,7 @@ void emit_tex(struct brw_wm_compile *c,
              struct brw_reg depth_payload,
              GLuint tex_idx,
              GLuint sampler,
-             GLboolean shadow);
+             bool shadow);
 void emit_txb(struct brw_wm_compile *c,
              struct brw_reg *dst,
              GLuint dst_flags,