i965: Use immediate float operands for some VS instructions.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_glsl.c

diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index e3e6f6633903be3b4ded92220c6ffbab3a194a80..88b885cb94147bc981e4f66ffc471a1c943f3052 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -23,6 +23,9 @@ GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp)
 {
     int i;
 
+    if (INTEL_DEBUG & DEBUG_GLSL_FORCE)
+       return GL_TRUE;
+
     for (i = 0; i < fp->Base.NumInstructions; i++) {
        const struct prog_instruction *inst = &fp->Base.Instructions[i];
        switch (inst->Opcode) {
@@ -289,6 +292,7 @@ reclaim_temps(struct brw_wm_compile *c)
  */
 static void prealloc_reg(struct brw_wm_compile *c)
 {
+    struct intel_context *intel = &c->func.brw->intel;
     int i, j;
     struct brw_reg reg;
     int urb_read_length = 0;
@@ -413,6 +417,43 @@ static void prealloc_reg(struct brw_wm_compile *c)
        }
     }
 
+    for (i = 0; i < c->nr_fp_insns; i++) {
+       const struct prog_instruction *inst = &c->prog_instructions[i];
+
+       switch (inst->Opcode) {
+       case WM_DELTAXY:
+           /* Allocate WM_DELTAXY destination on G45/GM45 to an
+            * even-numbered GRF if possible so that we can use the PLN
+            * instruction.
+            */
+           if (inst->DstReg.WriteMask == WRITEMASK_XY &&
+               !c->wm_regs[inst->DstReg.File][inst->DstReg.Index][0].inited &&
+               !c->wm_regs[inst->DstReg.File][inst->DstReg.Index][1].inited &&
+               (IS_G4X(intel->intelScreen->deviceID) || intel->gen == 5)) {
+               int grf;
+
+               for (grf = c->first_free_grf & ~1;
+                    grf < BRW_WM_MAX_GRF;
+                    grf += 2)
+               {
+                   if (!c->used_grf[grf] && !c->used_grf[grf + 1]) {
+                       c->used_grf[grf] = GL_TRUE;
+                       c->used_grf[grf + 1] = GL_TRUE;
+                       c->first_free_grf = grf + 2;  /* a guess */
+
+                       set_reg(c, inst->DstReg.File, inst->DstReg.Index, 0,
+                               brw_vec8_grf(grf, 0));
+                       set_reg(c, inst->DstReg.File, inst->DstReg.Index, 1,
+                               brw_vec8_grf(grf + 1, 0));
+                       break;
+                   }
+               }
+           }
+       default:
+           break;
+       }
+    }
+
     /* An instruction may reference up to three constants.
      * They'll be found in these registers.
      * XXX alloc these on demand!
@@ -529,12 +570,35 @@ static struct brw_reg get_src_reg(struct brw_wm_compile *c,
     const GLuint nr = 1;
     const GLuint component = GET_SWZ(src->Swizzle, channel);
 
-    /* Extended swizzle terms */
-    if (component == SWIZZLE_ZERO) {
-       return brw_imm_f(0.0F);
-    }
-    else if (component == SWIZZLE_ONE) {
-       return brw_imm_f(1.0F);
+    /* Only one immediate value can be used per native opcode, and it
+     * has be in the src1 slot, so not all Mesa instructions will get
+     * to take advantage of immediate constants.
+     */
+    if (brw_wm_arg_can_be_immediate(inst->Opcode, srcRegIndex)) {
+       const struct gl_program_parameter_list *params;
+
+       params = c->fp->program.Base.Parameters;
+
+       /* Extended swizzle terms */
+       if (component == SWIZZLE_ZERO) {
+         return brw_imm_f(0.0F);
+       } else if (component == SWIZZLE_ONE) {
+         if (src->Negate)
+            return brw_imm_f(-1.0F);
+         else
+            return brw_imm_f(1.0F);
+       }
+
+       if (src->File == PROGRAM_CONSTANT) {
+         float f = params->ParameterValues[src->Index][component];
+
+         if (src->Abs)
+            f = fabs(f);
+         if (src->Negate)
+            f = -f;
+
+         return brw_imm_f(f);
+       }
     }
 
     if (c->fp->use_const_buffer &&
@@ -2006,7 +2070,7 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
                   struct brw_instruction *inst0, *inst1;
                   GLuint br = 1;
 
-                  if (intel->is_ironlake)
+                  if (intel->gen == 5)
                      br = 2;
 
                  assert(loop_depth > 0);
@@ -2015,11 +2079,13 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
                   /* patch all the BREAK/CONT instructions from last BGNLOOP */
                   while (inst0 > loop_inst[loop_depth]) {
                      inst0--;
-                     if (inst0->header.opcode == BRW_OPCODE_BREAK) {
+                     if (inst0->header.opcode == BRW_OPCODE_BREAK &&
+                        inst0->bits3.if_else.jump_count == 0) {
                        inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
                        inst0->bits3.if_else.pop_count = 0;
                      }
-                     else if (inst0->header.opcode == BRW_OPCODE_CONTINUE) {
+                     else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
+                             inst0->bits3.if_else.jump_count == 0) {
                         inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
                         inst0->bits3.if_else.pop_count = 0;
                      }
@@ -2027,8 +2093,9 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
                }
                break;
            default:
-               printf("unsupported IR in fragment shader %d\n",
-                       inst->Opcode);
+               printf("unsupported opcode %d (%s) in fragment shader\n",
+                      inst->Opcode, inst->Opcode < MAX_OPCODE ?
+                      _mesa_opcode_string(inst->Opcode) : "unknown");
        }
 
        /* Release temporaries containing any unaliased source regs. */