i965: Add support for GL_ARB_seamless_cube_map

[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_glsl.c

diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index 3a68e05173c9eb007e98fd329b932f74ad2a9b85..a5b18ec7d76b332bed144e2c4d63403e5d3a660c 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -10,6 +10,9 @@ enum _subroutine {
     SUB_NOISE1, SUB_NOISE2, SUB_NOISE3, SUB_NOISE4
 };
 
+static struct brw_reg get_dst_reg(struct brw_wm_compile *c,
+                                  const struct prog_instruction *inst,
+                                  GLuint component);
 
 /**
  * Determine if the given fragment program uses GLSL features such
@@ -131,19 +134,6 @@ static void set_reg(struct brw_wm_compile *c, int file, int index,
     c->wm_regs[file][index][component].inited = GL_TRUE;
 }
 
-/**
- * Examine instruction's write mask to find index of first component
- * enabled for writing.
- */
-static int get_scalar_dst_index(const struct prog_instruction *inst)
-{
-    int i;
-    for (i = 0; i < 4; i++)
-       if (inst->DstReg.WriteMask & (1<<i))
-           break;
-    return i;
-}
-
 static struct brw_reg alloc_tmp(struct brw_wm_compile *c)
 {
     struct brw_reg reg;
@@ -403,6 +393,27 @@ static void prealloc_reg(struct brw_wm_compile *c)
     prealloc_grf(c, 126);
     prealloc_grf(c, 127);
 
+    for (i = 0; i < c->nr_fp_insns; i++) {
+       const struct prog_instruction *inst = &c->prog_instructions[i];
+       struct brw_reg dst[4];
+
+       switch (inst->Opcode) {
+       case OPCODE_TEX:
+       case OPCODE_TXB:
+           /* Allocate the channels of texture results contiguously,
+            * since they are written out that way by the sampler unit.
+            */
+           for (j = 0; j < 4; j++) {
+               dst[j] = get_dst_reg(c, inst, j);
+               if (j != 0)
+                   assert(dst[j].nr == dst[j - 1].nr + 1);
+           }
+           break;
+       default:
+           break;
+       }
+    }
+
     /* An instruction may reference up to three constants.
      * They'll be found in these registers.
      * XXX alloc these on demand!
@@ -640,23 +651,6 @@ static void invoke_subroutine( struct brw_wm_compile *c,
     }
 }
 
-static void emit_abs( struct brw_wm_compile *c,
-                      const struct prog_instruction *inst)
-{
-    int i;
-    struct brw_compile *p = &c->func;
-    brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
-    for (i = 0; i < 4; i++) {
-       if (inst->DstReg.WriteMask & (1<<i)) {
-           struct brw_reg src, dst;
-           dst = get_dst_reg(c, inst, i);
-           src = get_src_reg(c, inst, 0, i);
-           brw_MOV(p, dst, brw_abs(src));
-       }
-    }
-    brw_set_saturate(p, 0);
-}
-
 static void emit_trunc( struct brw_wm_compile *c,
                         const struct prog_instruction *inst)
 {
@@ -2834,9 +2828,6 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
            case WM_FRONTFACING:
                emit_frontfacing(c, inst);
                break;
-           case OPCODE_ABS:
-               emit_abs(c, inst);
-               break;
            case OPCODE_ADD:
                emit_add(c, inst);
                break;