i965/gen7: Fix shadow sampling in the old brw_wm_emit backend.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_iz.c

diff --git a/src/mesa/drivers/dri/i965/brw_wm_iz.c b/src/mesa/drivers/dri/i965/brw_wm_iz.c
index 7e2b1c79dedf1293604f533919ae0fa590be39d4..471ea1c18d68ac0e8cef6630cd8db569852a82b6 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_iz.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_iz.c
@@ -116,38 +116,56 @@ const struct {
  { C, 0, 1, 1, 1 } 
 };
 
-void brw_wm_lookup_iz( GLuint line_aa,
-                      GLuint lookup,
-                      GLboolean ps_uses_depth,
-                      struct brw_wm_prog_key *key )
+/**
+ * \param line_aa  AA_NEVER, AA_ALWAYS or AA_SOMETIMES
+ * \param lookup  bitmask of IZ_* flags
+ */
+void brw_wm_lookup_iz(struct intel_context *intel,
+                     struct brw_wm_compile *c)
 {
    GLuint reg = 2;
+   GLboolean kill_stats_promoted_workaround = GL_FALSE;
+   int lookup = c->key.iz_lookup;
+   bool uses_depth = (c->fp->program.Base.InputsRead &
+                     (1 << FRAG_ATTRIB_WPOS)) != 0;
 
    assert (lookup < IZ_BIT_MAX);
-      
+
+   /* Crazy workaround in the windowizer, which we need to track in
+    * our register allocation and render target writes.  See the "If
+    * statistics are enabled..." paragraph of 11.5.3.2: Early Depth
+    * Test Cases [Pre-DevGT] of the 3D Pipeline - Windower B-Spec.
+    */
+   if (c->key.stats_wm &&
+       (lookup & IZ_PS_KILL_ALPHATEST_BIT) &&
+       wm_iz_table[lookup].mode == P) {
+      kill_stats_promoted_workaround = GL_TRUE;
+   }
+
    if (lookup & IZ_PS_COMPUTES_DEPTH_BIT)
-      key->computes_depth = 1;
+      c->computes_depth = 1;
 
-   if (wm_iz_table[lookup].sd_present || ps_uses_depth) {
-      key->source_depth_reg = reg;
+   if (wm_iz_table[lookup].sd_present || uses_depth ||
+       kill_stats_promoted_workaround) {
+      c->source_depth_reg = reg;
       reg += 2;
    }
 
-   if (wm_iz_table[lookup].sd_to_rt)
-      key->source_depth_to_render_target = 1;
+   if (wm_iz_table[lookup].sd_to_rt || kill_stats_promoted_workaround)
+      c->source_depth_to_render_target = 1;
 
-   if (wm_iz_table[lookup].ds_present || line_aa != AA_NEVER) {
-      key->aa_dest_stencil_reg = reg;
-      key->runtime_check_aads_emit = (!wm_iz_table[lookup].ds_present &&
-                                     line_aa == AA_SOMETIMES);
+   if (wm_iz_table[lookup].ds_present || c->key.line_aa != AA_NEVER) {
+      c->aa_dest_stencil_reg = reg;
+      c->runtime_check_aads_emit = (!wm_iz_table[lookup].ds_present &&
+                                   c->key.line_aa == AA_SOMETIMES);
       reg++;
    }
 
    if (wm_iz_table[lookup].dd_present) {
-      key->dest_depth_reg = reg;
+      c->dest_depth_reg = reg;
       reg+=2;
    }
 
-   key->nr_depth_regs = (reg+1)/2;
+   c->nr_payload_regs = reg;
 }