i965: Convert PIPELINE_SELECT to OUT_BATCH style.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_pass1.c

diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass1.c b/src/mesa/drivers/dri/i965/brw_wm_pass1.c
index b44939402920083e2df8984e95268d7ea9100ccf..7d6a3fa9f12e38fd3640b26a141a8b45c687508e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_pass1.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass1.c
@@ -128,8 +128,7 @@ void brw_wm_pass1( struct brw_wm_compile *c )
       if (inst->opcode == WM_FB_WRITE) {
         track_arg(c, inst, 0, WRITEMASK_XYZW); 
         track_arg(c, inst, 1, WRITEMASK_XYZW); 
-        if (c->key.source_depth_to_render_target &&
-            c->key.computes_depth)
+        if (c->source_depth_to_render_target && c->computes_depth)
            track_arg(c, inst, 2, WRITEMASK_Z); 
         else
            track_arg(c, inst, 2, 0); 
@@ -158,6 +157,7 @@ void brw_wm_pass1( struct brw_wm_compile *c )
       case OPCODE_FLR:
       case OPCODE_FRC:
       case OPCODE_MOV:
+      case OPCODE_SSG:
       case OPCODE_SWZ:
       case OPCODE_TRUNC:
         read0 = writemask;
@@ -254,6 +254,11 @@ void brw_wm_pass1( struct brw_wm_compile *c )
         read2 = WRITEMASK_W; /* pixel w */
         break;
 
+      case OPCODE_DP2:
+        read0 = WRITEMASK_XY;
+        read1 = WRITEMASK_XY;
+        break;
+
       case OPCODE_DP3: 
         read0 = WRITEMASK_XYZ;
         read1 = WRITEMASK_XYZ;
@@ -275,7 +280,6 @@ void brw_wm_pass1( struct brw_wm_compile *c )
 
       case OPCODE_DST:
       case WM_FRONTFACING:
-      case OPCODE_KIL_NV:
       default:
         break;
       }
@@ -285,7 +289,7 @@ void brw_wm_pass1( struct brw_wm_compile *c )
       track_arg(c, inst, 2, read2);
    }
 
-   if (INTEL_DEBUG & DEBUG_WM) {
+   if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
       brw_wm_print_program(c, "pass1");
    }
 }