i965: Add HiZ operation state to brw_context

[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_pass1.c

diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass1.c b/src/mesa/drivers/dri/i965/brw_wm_pass1.c
index 962515a99e905590d5a9b613882826a1fea12111..ee7a627455f9b3762c004d3234ea1cc3d78ad4dc 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_pass1.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass1.c
@@ -93,8 +93,10 @@ static GLuint get_texcoord_mask( GLuint tex_idx )
    case TEXTURE_1D_INDEX:
       return WRITEMASK_X;
    case TEXTURE_2D_INDEX:
+   case TEXTURE_1D_ARRAY_INDEX:
       return WRITEMASK_XY;
    case TEXTURE_3D_INDEX:
+   case TEXTURE_2D_ARRAY_INDEX:
       return WRITEMASK_XYZ;
    case TEXTURE_CUBE_INDEX:
       return WRITEMASK_XYZ;
@@ -128,8 +130,7 @@ void brw_wm_pass1( struct brw_wm_compile *c )
       if (inst->opcode == WM_FB_WRITE) {
         track_arg(c, inst, 0, WRITEMASK_XYZW); 
         track_arg(c, inst, 1, WRITEMASK_XYZW); 
-        if (c->key.source_depth_to_render_target &&
-            c->key.computes_depth)
+        if (c->source_depth_to_render_target && c->computes_depth)
            track_arg(c, inst, 2, WRITEMASK_Z); 
         else
            track_arg(c, inst, 2, 0); 
@@ -281,7 +282,6 @@ void brw_wm_pass1( struct brw_wm_compile *c )
 
       case OPCODE_DST:
       case WM_FRONTFACING:
-      case OPCODE_KIL_NV:
       default:
         break;
       }
@@ -291,7 +291,7 @@ void brw_wm_pass1( struct brw_wm_compile *c )
       track_arg(c, inst, 2, read2);
    }
 
-   if (INTEL_DEBUG & DEBUG_WM) {
+   if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
       brw_wm_print_program(c, "pass1");
    }
 }