intel: Add a batch flush between front-buffer downsample and X protocol.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_state.c

diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index f221846f0c88ee164f01a907d388be71c5dc75cc..404fdadbe63773f46ea8b46b5fd70d4dc40e48e6 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -110,7 +110,15 @@ brw_upload_wm_unit(struct brw_context *brw)
                        (wm->wm9.grf_reg_count_2 << 1)) >> 6;
 
    wm->thread1.depth_coef_urb_read_offset = 1;
-   wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
+   /* Use ALT floating point mode for ARB fragment programs, because they
+    * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
+    * rendering, CurrentFragmentProgram is used for this check to
+    * differentiate between the GLSL and non-GLSL cases.
+    */
+   if (ctx->Shader.CurrentFragmentProgram == NULL)
+      wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
+   else
+      wm->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754;
 
    wm->thread1.binding_table_entry_count = 0;
 
@@ -136,13 +144,13 @@ brw_upload_wm_unit(struct brw_context *brw)
       wm->wm4.sampler_count = 0; /* hardware requirement */
    else {
       /* CACHE_NEW_SAMPLER */
-      wm->wm4.sampler_count = (brw->sampler.count + 1) / 4;
+      wm->wm4.sampler_count = (brw->wm.sampler_count + 1) / 4;
    }
 
-   if (brw->sampler.count) {
+   if (brw->wm.sampler_count) {
       /* reloc */
       wm->wm4.sampler_state_pointer = (brw->batch.bo->offset +
-                                      brw->sampler.offset) >> 5;
+                                      brw->wm.sampler_offset) >> 5;
    } else {
       wm->wm4.sampler_state_pointer = 0;
    }
@@ -217,13 +225,13 @@ brw_upload_wm_unit(struct brw_context *brw)
    }
 
    /* Emit sampler state relocation */
-   if (brw->sampler.count != 0) {
+   if (brw->wm.sampler_count != 0) {
       drm_intel_bo_emit_reloc(brw->batch.bo,
                              brw->wm.state_offset +
                              offsetof(struct brw_wm_unit_state, wm4),
-                             brw->batch.bo, (brw->sampler.offset |
-                                               wm->wm4.stats_enable |
-                                               (wm->wm4.sampler_count << 2)),
+                             brw->batch.bo, (brw->wm.sampler_offset |
+                                              wm->wm4.stats_enable |
+                                              (wm->wm4.sampler_count << 2)),
                              I915_GEM_DOMAIN_INSTRUCTION, 0);
    }