unsigned int curbe_offset;
unsigned int urb_size;
- unsigned int max_threads;
-
unsigned int nr_surfaces, sampler_count;
GLboolean uses_depth, computes_depth, uses_kill, is_glsl;
GLboolean polygon_stipple, stats_wm, line_stipple, offset_enable;
static void
wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key)
{
- GLcontext *ctx = &brw->intel.ctx;
+ struct gl_context *ctx = &brw->intel.ctx;
const struct gl_fragment_program *fp = brw->fragment_program;
const struct brw_fragment_program *bfp = (struct brw_fragment_program *) fp;
struct intel_context *intel = &brw->intel;
memset(key, 0, sizeof(*key));
- if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
- key->max_threads = 1;
- else {
- /* WM maximum threads is number of EUs times number of threads per EU. */
- if (BRW_IS_IGDNG(brw))
- key->max_threads = 12 * 6;
- else if (BRW_IS_G4X(brw))
- key->max_threads = 10 * 5;
- else
- key->max_threads = 8 * 4;
- }
-
/* CACHE_NEW_WM_PROG */
key->total_grf = brw->wm.prog_data->total_grf;
key->urb_entry_read_length = brw->wm.prog_data->urb_read_length;
/* as far as we can tell */
key->computes_depth =
- (fp->Base.OutputsWritten & (1 << FRAG_RESULT_DEPTH)) != 0;
+ (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
+ /* BRW_NEW_DEPTH_BUFFER
+ * Override for NULL depthbuffer case, required by the Pixel Shader Computed
+ * Depth field.
+ */
+ if (brw->state.depth_region == NULL)
+ key->computes_depth = 0;
/* _NEW_COLOR */
key->uses_kill = fp->UsesKill || ctx->Color.AlphaEnabled;
key->is_glsl = bfp->isGLSL;
- /* temporary sanity check assertion */
- ASSERT(bfp->isGLSL == brw_wm_is_glsl(fp));
+ /* If using the fragment shader backend, the program is always
+ * 8-wide.
+ */
+ if (ctx->Shader.CurrentProgram) {
+ struct brw_shader *shader = (struct brw_shader *)
+ ctx->Shader.CurrentProgram->_LinkedShaders[MESA_SHADER_FRAGMENT];
+
+ if (shader != NULL && shader->ir != NULL) {
+ key->is_glsl = GL_TRUE;
+ }
+ }
/* _NEW_DEPTH */
key->stats_wm = intel->stats_wm;
/**
* Setup wm hardware state. See page 225 of Volume 2
*/
-static dri_bo *
+static drm_intel_bo *
wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
- dri_bo **reloc_bufs)
+ drm_intel_bo **reloc_bufs)
{
+ struct intel_context *intel = &brw->intel;
struct brw_wm_unit_state wm;
- dri_bo *bo;
+ drm_intel_bo *bo;
memset(&wm, 0, sizeof(wm));
wm.thread1.depth_coef_urb_read_offset = 1;
wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
- if (BRW_IS_IGDNG(brw))
+ if (intel->gen == 5)
wm.thread1.binding_table_entry_count = 0; /* hardware requirement */
else
wm.thread1.binding_table_entry_count = key->nr_surfaces;
wm.thread3.const_urb_entry_read_length = key->curb_entry_read_length;
wm.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
- if (BRW_IS_IGDNG(brw))
+ if (intel->gen == 5)
wm.wm4.sampler_count = 0; /* hardware requirement */
else
wm.wm4.sampler_count = (key->sampler_count + 1) / 4;
else
wm.wm5.enable_16_pix = 1;
- wm.wm5.max_threads = key->max_threads - 1;
+ wm.wm5.max_threads = brw->wm_max_threads - 1;
wm.wm5.thread_dispatch_enable = 1; /* AKA: color_write */
wm.wm5.legacy_line_rast = 0;
wm.wm5.legacy_global_depth_bias = 0;
bo = brw_upload_cache(&brw->cache, BRW_WM_UNIT,
key, sizeof(*key),
reloc_bufs, 3,
- &wm, sizeof(wm),
- NULL, NULL);
+ &wm, sizeof(wm));
/* Emit WM program relocation */
- dri_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- wm.thread0.grf_reg_count << 1,
- offsetof(struct brw_wm_unit_state, thread0),
- brw->wm.prog_bo);
+ drm_intel_bo_emit_reloc(bo, offsetof(struct brw_wm_unit_state, thread0),
+ brw->wm.prog_bo, wm.thread0.grf_reg_count << 1,
+ I915_GEM_DOMAIN_INSTRUCTION, 0);
/* Emit scratch space relocation */
if (key->total_scratch != 0) {
- dri_bo_emit_reloc(bo,
- 0, 0,
- wm.thread2.per_thread_scratch_space,
- offsetof(struct brw_wm_unit_state, thread2),
- brw->wm.scratch_bo);
+ drm_intel_bo_emit_reloc(bo, offsetof(struct brw_wm_unit_state, thread2),
+ brw->wm.scratch_bo,
+ wm.thread2.per_thread_scratch_space,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
}
/* Emit sampler state relocation */
if (key->sampler_count != 0) {
- dri_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- wm.wm4.stats_enable | (wm.wm4.sampler_count << 2),
- offsetof(struct brw_wm_unit_state, wm4),
- brw->wm.sampler_bo);
+ drm_intel_bo_emit_reloc(bo, offsetof(struct brw_wm_unit_state, wm4),
+ brw->wm.sampler_bo, (wm.wm4.stats_enable |
+ (wm.wm4.sampler_count << 2)),
+ I915_GEM_DOMAIN_INSTRUCTION, 0);
}
return bo;
{
struct intel_context *intel = &brw->intel;
struct brw_wm_unit_key key;
- dri_bo *reloc_bufs[3];
+ drm_intel_bo *reloc_bufs[3];
wm_unit_populate_key(brw, &key);
/* Allocate the necessary scratch space if we haven't already. Don't
*/
assert(key.total_scratch <= 12 * 1024);
if (key.total_scratch) {
- GLuint total = key.total_scratch * key.max_threads;
+ GLuint total = key.total_scratch * brw->wm_max_threads;
if (brw->wm.scratch_bo && total > brw->wm.scratch_bo->size) {
- dri_bo_unreference(brw->wm.scratch_bo);
+ drm_intel_bo_unreference(brw->wm.scratch_bo);
brw->wm.scratch_bo = NULL;
}
if (brw->wm.scratch_bo == NULL) {
- brw->wm.scratch_bo = dri_bo_alloc(intel->bufmgr,
- "wm scratch",
- total,
- 4096);
+ brw->wm.scratch_bo = drm_intel_bo_alloc(intel->bufmgr,
+ "wm scratch",
+ total,
+ 4096);
}
}
reloc_bufs[1] = brw->wm.scratch_bo;
reloc_bufs[2] = brw->wm.sampler_bo;
- dri_bo_unreference(brw->wm.state_bo);
+ drm_intel_bo_unreference(brw->wm.state_bo);
brw->wm.state_bo = brw_search_cache(&brw->cache, BRW_WM_UNIT,
&key, sizeof(key),
reloc_bufs, 3,
.brw = (BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_CURBE_OFFSETS |
+ BRW_NEW_DEPTH_BUFFER |
BRW_NEW_NR_WM_SURFACES),
.cache = (CACHE_NEW_WM_PROG |