i965/fs: Fix signedness of local variables and arguments of emit_(un)spill.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_state.c

diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 0dee1f857bbbeb7a3d80eb5de9edd9d37f2515a5..bf1bdc9948f67282c52f29b6e502e0912d7386c2 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -31,6 +31,7 @@
 
 
 
+#include "intel_batchbuffer.h"
 #include "intel_fbo.h"
 #include "brw_context.h"
 #include "brw_state.h"
@@ -47,7 +48,7 @@ brw_color_buffer_write_enabled(struct brw_context *brw)
    struct gl_context *ctx = &brw->ctx;
    /* BRW_NEW_FRAGMENT_PROGRAM */
    const struct gl_fragment_program *fp = brw->fragment_program;
-   int i;
+   unsigned i;
 
    /* _NEW_BUFFERS */
    for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
@@ -85,33 +86,39 @@ brw_upload_wm_unit(struct brw_context *brw)
                        sizeof(*wm), 32, &brw->wm.base.state_offset);
    memset(wm, 0, sizeof(*wm));
 
-   if (prog_data->prog_offset_16) {
+   if (prog_data->dispatch_8 && prog_data->dispatch_16) {
       /* These two fields should be the same pre-gen6, which is why we
        * only have one hardware field to program for both dispatch
        * widths.
        */
       assert(prog_data->base.dispatch_grf_start_reg ==
-            prog_data->dispatch_grf_start_reg_16);
+            prog_data->dispatch_grf_start_reg_2);
    }
 
    /* BRW_NEW_PROGRAM_CACHE | BRW_NEW_FS_PROG_DATA */
-   wm->thread0.grf_reg_count = prog_data->reg_blocks;
-   wm->wm9.grf_reg_count_2 = prog_data->reg_blocks_16;
-
-   wm->thread0.kernel_start_pointer =
-      brw_program_reloc(brw,
-                       brw->wm.base.state_offset +
-                       offsetof(struct brw_wm_unit_state, thread0),
-                       brw->wm.base.prog_offset +
-                       (wm->thread0.grf_reg_count << 1)) >> 6;
-
-   wm->wm9.kernel_start_pointer_2 =
-      brw_program_reloc(brw,
-                       brw->wm.base.state_offset +
-                       offsetof(struct brw_wm_unit_state, wm9),
-                       brw->wm.base.prog_offset +
-                       prog_data->prog_offset_16 +
-                       (wm->wm9.grf_reg_count_2 << 1)) >> 6;
+   wm->wm5.enable_8_pix = prog_data->dispatch_8;
+   wm->wm5.enable_16_pix = prog_data->dispatch_16;
+
+   if (prog_data->dispatch_8 || prog_data->dispatch_16) {
+      wm->thread0.grf_reg_count = prog_data->reg_blocks_0;
+      wm->thread0.kernel_start_pointer =
+         brw_program_reloc(brw,
+                           brw->wm.base.state_offset +
+                           offsetof(struct brw_wm_unit_state, thread0),
+                           brw->wm.base.prog_offset +
+                           (wm->thread0.grf_reg_count << 1)) >> 6;
+   }
+
+   if (prog_data->prog_offset_2) {
+      wm->wm9.grf_reg_count_2 = prog_data->reg_blocks_2;
+      wm->wm9.kernel_start_pointer_2 =
+         brw_program_reloc(brw,
+                           brw->wm.base.state_offset +
+                           offsetof(struct brw_wm_unit_state, wm9),
+                           brw->wm.base.prog_offset +
+                           prog_data->prog_offset_2 +
+                           (wm->wm9.grf_reg_count_2 << 1)) >> 6;
+   }
 
    wm->thread1.depth_coef_urb_read_offset = 1;
    if (prog_data->base.use_alt_mode)
@@ -157,8 +164,7 @@ brw_upload_wm_unit(struct brw_context *brw)
    }
 
    /* BRW_NEW_FRAGMENT_PROGRAM */
-   wm->wm5.program_uses_depth = (fp->Base.InputsRead &
-                                (1 << VARYING_SLOT_POS)) != 0;
+   wm->wm5.program_uses_depth = prog_data->uses_src_depth;
    wm->wm5.program_computes_depth = (fp->Base.OutputsWritten &
                                     BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
    /* _NEW_BUFFERS
@@ -172,10 +178,6 @@ brw_upload_wm_unit(struct brw_context *brw)
    wm->wm5.program_uses_killpixel =
       prog_data->uses_kill || ctx->Color.AlphaEnabled;
 
-   wm->wm5.enable_8_pix = 1;
-   if (prog_data->prog_offset_16)
-      wm->wm5.enable_16_pix = 1;
-
    wm->wm5.max_threads = brw->max_wm_threads - 1;
 
    /* _NEW_BUFFERS | _NEW_COLOR */
@@ -197,7 +199,7 @@ brw_upload_wm_unit(struct brw_context *brw)
    /* _NEW_POLYGON */
    if (ctx->Polygon.OffsetFill) {
       wm->wm5.depth_offset = 1;
-      /* Something wierd going on with legacy_global_depth_bias,
+      /* Something weird going on with legacy_global_depth_bias,
        * offset_constant, scaling and MRD.  This value passes glean
        * but gives some odd results elsewere (eg. the
        * quad-offset-units test).
@@ -237,7 +239,17 @@ brw_upload_wm_unit(struct brw_context *brw)
                              I915_GEM_DOMAIN_INSTRUCTION, 0);
    }
 
-   brw->state.dirty.brw |= BRW_NEW_GEN4_UNIT_STATE;
+   brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
+
+   /* _NEW_POLGYON */
+   if (brw->wm.offset_clamp != ctx->Polygon.OffsetClamp) {
+      BEGIN_BATCH(2);
+      OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
+      OUT_BATCH_F(ctx->Polygon.OffsetClamp);
+      ADVANCE_BATCH();
+
+      brw->wm.offset_clamp = ctx->Polygon.OffsetClamp;
+   }
 }
 
 const struct brw_tracked_state brw_wm_unit = {
@@ -248,6 +260,7 @@ const struct brw_tracked_state brw_wm_unit = {
               _NEW_POLYGON |
               _NEW_POLYGONSTIPPLE,
       .brw = BRW_NEW_BATCH |
+             BRW_NEW_BLORP |
              BRW_NEW_CURBE_OFFSETS |
              BRW_NEW_FRAGMENT_PROGRAM |
              BRW_NEW_FS_PROG_DATA |