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i965: Allocate dummy slots for point sprites before computing VUE map.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_state.c
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index a91ae511b7f87186410fc765357242c6bac5ec8a..dd67795e74311127b0fc76c7bb34d94517ceeb9e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -31,6 +31,7 @@
                    
 
 
+#include "intel_fbo.h"
 #include "brw_context.h"
 #include "brw_state.h"
 #include "brw_defines.h"
@@ -70,14 +71,15 @@ brw_color_buffer_write_enabled(struct brw_context *brw)
  * Setup wm hardware state.  See page 225 of Volume 2
  */
 static void
-brw_prepare_wm_unit(struct brw_context *brw)
+brw_upload_wm_unit(struct brw_context *brw)
 {
    struct intel_context *intel = &brw->intel;
    struct gl_context *ctx = &intel->ctx;
    const struct gl_fragment_program *fp = brw->fragment_program;
    struct brw_wm_unit_state *wm;
 
-   wm = brw_state_batch(brw, sizeof(*wm), 32, &brw->wm.state_offset);
+   wm = brw_state_batch(brw, AUB_TRACE_WM_STATE,
+                       sizeof(*wm), 32, &brw->wm.state_offset);
    memset(wm, 0, sizeof(*wm));
 
    if (brw->wm.prog_data->prog_offset_16) {
@@ -89,22 +91,29 @@ brw_prepare_wm_unit(struct brw_context *brw)
             brw->wm.prog_data->first_curbe_grf_16);
    }
 
-   /* CACHE_NEW_WM_PROG */
-   wm->thread0.grf_reg_count = ALIGN(brw->wm.prog_data->total_grf, 16) / 16 - 1;
-   wm->wm9.grf_reg_count_2 = ALIGN(brw->wm.prog_data->total_grf_16, 16) / 16 - 1;
-   wm->thread0.kernel_start_pointer = brw->wm.prog_bo->offset >> 6; /* reloc */
-   /* reloc */
-   wm->wm9.kernel_start_pointer_2 = (brw->wm.prog_bo->offset +
-                                    brw->wm.prog_data->prog_offset_16) >> 6;
+   /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_WM_PROG */
+   wm->thread0.grf_reg_count = brw->wm.prog_data->reg_blocks;
+   wm->wm9.grf_reg_count_2 = brw->wm.prog_data->reg_blocks_16;
+
+   wm->thread0.kernel_start_pointer =
+      brw_program_reloc(brw,
+                       brw->wm.state_offset +
+                       offsetof(struct brw_wm_unit_state, thread0),
+                       brw->wm.prog_offset +
+                       (wm->thread0.grf_reg_count << 1)) >> 6;
+
+   wm->wm9.kernel_start_pointer_2 =
+      brw_program_reloc(brw,
+                       brw->wm.state_offset +
+                       offsetof(struct brw_wm_unit_state, wm9),
+                       brw->wm.prog_offset +
+                       brw->wm.prog_data->prog_offset_16 +
+                       (wm->wm9.grf_reg_count_2 << 1)) >> 6;
+
    wm->thread1.depth_coef_urb_read_offset = 1;
    wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 
-   if (intel->gen == 5)
-      wm->thread1.binding_table_entry_count = 0; /* hardware requirement */
-   else {
-      /* BRW_NEW_NR_SURFACES */
-      wm->thread1.binding_table_entry_count = brw->wm.nr_surfaces;
-   }
+   wm->thread1.binding_table_entry_count = 0;
 
    if (brw->wm.prog_data->total_scratch != 0) {
       wm->thread2.scratch_space_base_pointer =
@@ -128,13 +137,13 @@ brw_prepare_wm_unit(struct brw_context *brw)
       wm->wm4.sampler_count = 0; /* hardware requirement */
    else {
       /* CACHE_NEW_SAMPLER */
-      wm->wm4.sampler_count = (brw->wm.sampler_count + 1) / 4;
+      wm->wm4.sampler_count = (brw->sampler.count + 1) / 4;
    }
 
-   if (brw->wm.sampler_count) {
+   if (brw->sampler.count) {
       /* reloc */
       wm->wm4.sampler_state_pointer = (intel->batch.bo->offset +
-                                      brw->wm.sampler_offset) >> 5;
+                                      brw->sampler.offset) >> 5;
    } else {
       wm->wm4.sampler_state_pointer = 0;
    }
@@ -144,11 +153,11 @@ brw_prepare_wm_unit(struct brw_context *brw)
                                 (1 << FRAG_ATTRIB_WPOS)) != 0;
    wm->wm5.program_computes_depth = (fp->Base.OutputsWritten &
                                     BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
-   /* BRW_NEW_DEPTH_BUFFER
+   /* _NEW_BUFFERS
     * Override for NULL depthbuffer case, required by the Pixel Shader Computed
     * Depth field.
     */
-   if (brw->state.depth_region == NULL)
+   if (!intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH))
       wm->wm5.program_computes_depth = 0;
 
    /* _NEW_COLOR */
@@ -160,9 +169,9 @@ brw_prepare_wm_unit(struct brw_context *brw)
     * If using the fragment shader backend, the program is always
     * 8-wide.  If not, it's always 16.
     */
-   if (ctx->Shader.CurrentFragmentProgram) {
+   if (ctx->Shader._CurrentFragmentProgram) {
       struct brw_shader *shader = (struct brw_shader *)
-        ctx->Shader.CurrentFragmentProgram->_LinkedShaders[MESA_SHADER_FRAGMENT];
+        ctx->Shader._CurrentFragmentProgram->_LinkedShaders[MESA_SHADER_FRAGMENT];
 
       if (shader != NULL && shader->ir != NULL) {
         wm->wm5.enable_8_pix = 1;
@@ -173,7 +182,7 @@ brw_prepare_wm_unit(struct brw_context *brw)
    if (!wm->wm5.enable_8_pix)
       wm->wm5.enable_16_pix = 1;
 
-   wm->wm5.max_threads = brw->wm_max_threads - 1;
+   wm->wm5.max_threads = brw->max_wm_threads - 1;
 
    /* _NEW_BUFFERS | _NEW_COLOR */
    if (brw_color_buffer_write_enabled(brw) ||
@@ -213,23 +222,6 @@ brw_prepare_wm_unit(struct brw_context *brw)
    if (unlikely(INTEL_DEBUG & DEBUG_STATS) || intel->stats_wm)
       wm->wm4.stats_enable = 1;
 
-   /* Emit WM program relocation */
-   drm_intel_bo_emit_reloc(intel->batch.bo,
-                          brw->wm.state_offset +
-                          offsetof(struct brw_wm_unit_state, thread0),
-                          brw->wm.prog_bo, wm->thread0.grf_reg_count << 1,
-                          I915_GEM_DOMAIN_INSTRUCTION, 0);
-
-   if (brw->wm.prog_data->prog_offset_16) {
-      drm_intel_bo_emit_reloc(intel->batch.bo,
-                             brw->wm.state_offset +
-                             offsetof(struct brw_wm_unit_state, wm9),
-                             brw->wm.prog_bo,
-                             ((wm->wm9.grf_reg_count_2 << 1) +
-                              brw->wm.prog_data->prog_offset_16),
-                             I915_GEM_DOMAIN_INSTRUCTION, 0);
-   }
-
    /* Emit scratch space relocation */
    if (brw->wm.prog_data->total_scratch != 0) {
       drm_intel_bo_emit_reloc(intel->batch.bo,
@@ -241,11 +233,11 @@ brw_prepare_wm_unit(struct brw_context *brw)
    }
 
    /* Emit sampler state relocation */
-   if (brw->wm.sampler_count != 0) {
+   if (brw->sampler.count != 0) {
       drm_intel_bo_emit_reloc(intel->batch.bo,
                              brw->wm.state_offset +
                              offsetof(struct brw_wm_unit_state, wm4),
-                             intel->batch.bo, (brw->wm.sampler_offset |
+                             intel->batch.bo, (brw->sampler.offset |
                                                wm->wm4.stats_enable |
                                                (wm->wm4.sampler_count << 2)),
                              I915_GEM_DOMAIN_INSTRUCTION, 0);
@@ -264,14 +256,13 @@ const struct brw_tracked_state brw_wm_unit = {
               _NEW_BUFFERS),
 
       .brw = (BRW_NEW_BATCH |
+             BRW_NEW_PROGRAM_CACHE |
              BRW_NEW_FRAGMENT_PROGRAM |
-             BRW_NEW_CURBE_OFFSETS |
-             BRW_NEW_DEPTH_BUFFER |
-             BRW_NEW_NR_WM_SURFACES),
+             BRW_NEW_CURBE_OFFSETS),
 
       .cache = (CACHE_NEW_WM_PROG |
                CACHE_NEW_SAMPLER)
    },
-   .prepare = brw_prepare_wm_unit,
+   .emit = brw_upload_wm_unit,
 };