i965: Add HiZ operation state to brw_context

[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_state.c

diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index c820ce48c2947bf132173581b5d432b83880b213..e1791c20ea72de92b6e635f3726c6ad81ec0f353 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -71,7 +71,7 @@ brw_color_buffer_write_enabled(struct brw_context *brw)
  * Setup wm hardware state.  See page 225 of Volume 2
  */
 static void
-brw_prepare_wm_unit(struct brw_context *brw)
+brw_upload_wm_unit(struct brw_context *brw)
 {
    struct intel_context *intel = &brw->intel;
    struct gl_context *ctx = &intel->ctx;
@@ -113,12 +113,7 @@ brw_prepare_wm_unit(struct brw_context *brw)
    wm->thread1.depth_coef_urb_read_offset = 1;
    wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 
-   if (intel->gen == 5)
-      wm->thread1.binding_table_entry_count = 0; /* hardware requirement */
-   else {
-      /* BRW_NEW_NR_SURFACES */
-      wm->thread1.binding_table_entry_count = brw->wm.nr_surfaces;
-   }
+   wm->thread1.binding_table_entry_count = 0;
 
    if (brw->wm.prog_data->total_scratch != 0) {
       wm->thread2.scratch_space_base_pointer =
@@ -142,13 +137,13 @@ brw_prepare_wm_unit(struct brw_context *brw)
       wm->wm4.sampler_count = 0; /* hardware requirement */
    else {
       /* CACHE_NEW_SAMPLER */
-      wm->wm4.sampler_count = (brw->wm.sampler_count + 1) / 4;
+      wm->wm4.sampler_count = (brw->sampler.count + 1) / 4;
    }
 
-   if (brw->wm.sampler_count) {
+   if (brw->sampler.count) {
       /* reloc */
       wm->wm4.sampler_state_pointer = (intel->batch.bo->offset +
-                                      brw->wm.sampler_offset) >> 5;
+                                      brw->sampler.offset) >> 5;
    } else {
       wm->wm4.sampler_state_pointer = 0;
    }
@@ -187,7 +182,7 @@ brw_prepare_wm_unit(struct brw_context *brw)
    if (!wm->wm5.enable_8_pix)
       wm->wm5.enable_16_pix = 1;
 
-   wm->wm5.max_threads = brw->wm_max_threads - 1;
+   wm->wm5.max_threads = brw->max_wm_threads - 1;
 
    /* _NEW_BUFFERS | _NEW_COLOR */
    if (brw_color_buffer_write_enabled(brw) ||
@@ -238,11 +233,11 @@ brw_prepare_wm_unit(struct brw_context *brw)
    }
 
    /* Emit sampler state relocation */
-   if (brw->wm.sampler_count != 0) {
+   if (brw->sampler.count != 0) {
       drm_intel_bo_emit_reloc(intel->batch.bo,
                              brw->wm.state_offset +
                              offsetof(struct brw_wm_unit_state, wm4),
-                             intel->batch.bo, (brw->wm.sampler_offset |
+                             intel->batch.bo, (brw->sampler.offset |
                                                wm->wm4.stats_enable |
                                                (wm->wm4.sampler_count << 2)),
                              I915_GEM_DOMAIN_INSTRUCTION, 0);
@@ -263,12 +258,11 @@ const struct brw_tracked_state brw_wm_unit = {
       .brw = (BRW_NEW_BATCH |
              BRW_NEW_PROGRAM_CACHE |
              BRW_NEW_FRAGMENT_PROGRAM |
-             BRW_NEW_CURBE_OFFSETS |
-             BRW_NEW_NR_WM_SURFACES),
+             BRW_NEW_CURBE_OFFSETS),
 
       .cache = (CACHE_NEW_WM_PROG |
                CACHE_NEW_SAMPLER)
    },
-   .prepare = brw_prepare_wm_unit,
+   .emit = brw_upload_wm_unit,
 };