static void
brw_update_buffer_texture_surface(struct gl_context *ctx,
unsigned unit,
- uint32_t *binding_table,
- unsigned surf_index)
+ uint32_t *surf_offset)
{
struct brw_context *brw = brw_context(ctx);
struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
}
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 6 * 4, 32, &binding_table[surf_index]);
+ 6 * 4, 32, surf_offset);
surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
(brw_format_for_mesa_format(format) << BRW_SURFACE_FORMAT_SHIFT));
/* Emit relocation to surface contents. */
drm_intel_bo_emit_reloc(brw->batch.bo,
- binding_table[surf_index] + 4,
+ *surf_offset + 4,
bo, 0, I915_GEM_DOMAIN_SAMPLER, 0);
int w = intel_obj->Base.Size / texel_size;
static void
brw_update_texture_surface(struct gl_context *ctx,
unsigned unit,
- uint32_t *binding_table,
- unsigned surf_index)
+ uint32_t *surf_offset)
{
struct brw_context *brw = brw_context(ctx);
struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
struct intel_texture_object *intelObj = intel_texture_object(tObj);
struct intel_mipmap_tree *mt = intelObj->mt;
struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
+ struct intel_texture_image *intel_image = intel_texture_image(firstImage);
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
uint32_t *surf;
- uint32_t tile_x, tile_y;
if (tObj->Target == GL_TEXTURE_BUFFER) {
- brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
+ brw_update_buffer_texture_surface(ctx, unit, surf_offset);
return;
}
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 6 * 4, 32, &binding_table[surf_index]);
+ 6 * 4, 32, surf_offset);
surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
BRW_SURFACE_FORMAT_SHIFT));
surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */
- surf[1] += intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
- &tile_x, &tile_y);
- surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
+ surf[2] = ((intelObj->_MaxLevel - intel_image->mt->first_level) << BRW_SURFACE_LOD_SHIFT |
(mt->logical_width0 - 1) << BRW_SURFACE_WIDTH_SHIFT |
(mt->logical_height0 - 1) << BRW_SURFACE_HEIGHT_SHIFT);
surf[4] = brw_get_surface_num_multisamples(intelObj->mt->num_samples);
- assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
- /* Note that the low bits of these fields are missing, so
- * there's the possibility of getting in trouble.
- */
- assert(tile_x % 4 == 0);
- assert(tile_y % 2 == 0);
- surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
- (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
- (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
+ surf[5] = mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
/* Emit relocation to surface contents */
drm_intel_bo_emit_reloc(brw->batch.bo,
- binding_table[surf_index] + 4,
+ *surf_offset + 4,
intelObj->mt->region->bo,
surf[1] - intelObj->mt->region->bo->offset,
I915_GEM_DOMAIN_SAMPLER, 0);
surf[4] = 0;
surf[5] = 0;
- /* Emit relocation to surface contents. Section 5.1.1 of the gen4
- * bspec ("Data Cache") says that the data cache does not exist as
- * a separate cache and is just the sampler cache.
+ /* Emit relocation to surface contents. The 965 PRM, Volume 4, section
+ * 5.1.2 "Data Cache" says: "the data cache does not exist as a separate
+ * physical cache. It is mapped in hardware to the sampler cache."
*/
drm_intel_bo_emit_reloc(brw->batch.bo,
*out_offset + 4,
/* _NEW_BUFFERS */
const struct gl_framebuffer *fb = ctx->DrawBuffer;
- surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 6 * 4, 32, &brw->wm.surf_offset[unit]);
+ surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
+ &brw->wm.surf_offset[SURF_INDEX_DRAW(unit)]);
if (fb->Visual.samples > 1) {
/* On Gen6, null render targets seem to cause GPU hangs when
if (bo) {
drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.surf_offset[unit] + 4,
+ brw->wm.surf_offset[SURF_INDEX_DRAW(unit)] + 4,
bo, 0,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
}
region = irb->mt->region;
- surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 6 * 4, 32, &brw->wm.surf_offset[unit]);
+ surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
+ &brw->wm.surf_offset[SURF_INDEX_DRAW(unit)]);
format = brw->render_target_format[rb_format];
if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
}
drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.surf_offset[unit] + 4,
+ brw->wm.surf_offset[SURF_INDEX_DRAW(unit)] + 4,
region->bo,
surf[1] - region->bo->offset,
I915_GEM_DOMAIN_RENDER,
.emit = brw_update_renderbuffer_surfaces,
};
-/**
- * Construct SURFACE_STATE objects for enabled textures.
- */
+
static void
-brw_update_texture_surfaces(struct brw_context *brw)
+update_stage_texture_surfaces(struct brw_context *brw,
+ const struct gl_program *prog,
+ uint32_t *surf_offset)
{
- struct gl_context *ctx = &brw->ctx;
+ if (!prog)
+ return;
- /* BRW_NEW_VERTEX_PROGRAM and BRW_NEW_FRAGMENT_PROGRAM:
- * Unfortunately, we're stuck using the gl_program structs until the
- * ARB_fragment_program front-end gets converted to GLSL IR. These
- * have the downside that SamplerUnits is split and only contains the
- * mappings for samplers active in that stage.
- */
- struct gl_program *vs = (struct gl_program *) brw->vertex_program;
- struct gl_program *fs = (struct gl_program *) brw->fragment_program;
+ struct gl_context *ctx = &brw->ctx;
- unsigned num_samplers = _mesa_fls(vs->SamplersUsed | fs->SamplersUsed);
+ unsigned num_samplers = _mesa_fls(prog->SamplersUsed);
for (unsigned s = 0; s < num_samplers; s++) {
- brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(s)] = 0;
- brw->wm.surf_offset[SURF_INDEX_TEXTURE(s)] = 0;
+ surf_offset[s] = 0;
- if (vs->SamplersUsed & (1 << s)) {
- const unsigned unit = vs->SamplerUnits[s];
+ if (prog->SamplersUsed & (1 << s)) {
+ const unsigned unit = prog->SamplerUnits[s];
/* _NEW_TEXTURE */
if (ctx->Texture.Unit[unit]._ReallyEnabled) {
- brw->vtbl.update_texture_surface(ctx, unit,
- brw->vs.surf_offset,
- SURF_INDEX_VS_TEXTURE(s));
+ brw->vtbl.update_texture_surface(ctx, unit, surf_offset + s);
}
}
+ }
+}
- if (fs->SamplersUsed & (1 << s)) {
- const unsigned unit = fs->SamplerUnits[s];
- /* _NEW_TEXTURE */
- if (ctx->Texture.Unit[unit]._ReallyEnabled) {
- brw->vtbl.update_texture_surface(ctx, unit,
- brw->wm.surf_offset,
- SURF_INDEX_TEXTURE(s));
- }
- }
- }
+/**
+ * Construct SURFACE_STATE objects for enabled textures.
+ */
+static void
+brw_update_texture_surfaces(struct brw_context *brw)
+{
+ /* BRW_NEW_VERTEX_PROGRAM */
+ struct gl_program *vs = (struct gl_program *) brw->vertex_program;
+
+ /* BRW_NEW_GEOMETRY_PROGRAM */
+ struct gl_program *gs = (struct gl_program *) brw->geometry_program;
+
+ /* BRW_NEW_FRAGMENT_PROGRAM */
+ struct gl_program *fs = (struct gl_program *) brw->fragment_program;
+
+ /* _NEW_TEXTURE */
+ update_stage_texture_surfaces(brw, vs,
+ brw->vs.base.surf_offset +
+ SURF_INDEX_VEC4_TEXTURE(0));
+ update_stage_texture_surfaces(brw, gs,
+ brw->gs.base.surf_offset +
+ SURF_INDEX_VEC4_TEXTURE(0));
+ update_stage_texture_surfaces(brw, fs,
+ brw->wm.surf_offset +
+ SURF_INDEX_TEXTURE(0));
brw->state.dirty.brw |= BRW_NEW_SURFACES;
}
.mesa = _NEW_TEXTURE,
.brw = BRW_NEW_BATCH |
BRW_NEW_VERTEX_PROGRAM |
+ BRW_NEW_GEOMETRY_PROGRAM |
BRW_NEW_FRAGMENT_PROGRAM,
.cache = 0
},
gen7_create_shader_time_surface(brw, &brw->wm.surf_offset[SURF_INDEX_WM_SHADER_TIME]);
}
- /* Might want to calculate nr_surfaces first, to avoid taking up so much
- * space for the binding table.
- */
+ /* CACHE_NEW_WM_PROG */
+ unsigned entries = brw->wm.prog_data->binding_table_size;
bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
- sizeof(uint32_t) * BRW_MAX_WM_SURFACES,
+ sizeof(uint32_t) * entries,
32, &brw->wm.bind_bo_offset);
/* BRW_NEW_SURFACES */
- for (i = 0; i < BRW_MAX_WM_SURFACES; i++) {
+ for (i = 0; i < entries; i++) {
bind[i] = brw->wm.surf_offset[i];
}
.mesa = 0,
.brw = (BRW_NEW_BATCH |
BRW_NEW_SURFACES),
- .cache = 0
+ .cache = CACHE_NEW_WM_PROG
},
.emit = brw_upload_wm_binding_table,
};