#include "main/blend.h"
#include "main/mtypes.h"
#include "main/samplerobj.h"
+#include "main/shaderimage.h"
+#include "main/teximage.h"
#include "program/prog_parameter.h"
+#include "program/prog_instruction.h"
+#include "main/framebuffer.h"
+
+#include "isl/isl.h"
#include "intel_mipmap_tree.h"
#include "intel_batchbuffer.h"
#include "brw_defines.h"
#include "brw_wm.h"
+struct surface_state_info {
+ unsigned num_dwords;
+ unsigned ss_align; /* Required alignment of RENDER_SURFACE_STATE in bytes */
+ unsigned reloc_dw;
+ unsigned aux_reloc_dw;
+ unsigned tex_mocs;
+ unsigned rb_mocs;
+};
+
+static const struct surface_state_info surface_state_infos[] = {
+ [4] = {6, 32, 1, 0},
+ [5] = {6, 32, 1, 0},
+ [6] = {6, 32, 1, 0},
+ [7] = {8, 32, 1, 6, GEN7_MOCS_L3, GEN7_MOCS_L3},
+ [8] = {13, 64, 8, 10, BDW_MOCS_WB, BDW_MOCS_PTE},
+ [9] = {16, 64, 8, 10, SKL_MOCS_WB, SKL_MOCS_PTE},
+};
+
+void
+brw_emit_surface_state(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ const struct isl_view *view,
+ uint32_t mocs, bool for_gather,
+ uint32_t *surf_offset, int surf_index,
+ unsigned read_domains, unsigned write_domains)
+{
+ const struct surface_state_info ss_info = surface_state_infos[brw->gen];
+
+ struct isl_surf surf;
+ intel_miptree_get_isl_surf(brw, mt, &surf);
+
+ union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } };
+
+ struct isl_surf *aux_surf = NULL, aux_surf_s;
+ uint64_t aux_offset = 0;
+ enum isl_aux_usage aux_usage = ISL_AUX_USAGE_NONE;
+ if (mt->mcs_mt &&
+ ((view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) ||
+ mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_RESOLVED)) {
+ intel_miptree_get_aux_isl_surf(brw, mt, &aux_surf_s, &aux_usage);
+ aux_surf = &aux_surf_s;
+ assert(mt->mcs_mt->offset == 0);
+ aux_offset = mt->mcs_mt->bo->offset64;
+
+ /* We only really need a clear color if we also have an auxiliary
+ * surfacae. Without one, it does nothing.
+ */
+ clear_color = intel_miptree_get_isl_clear_color(brw, mt);
+ }
+
+ uint32_t *dw = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ ss_info.num_dwords * 4, ss_info.ss_align,
+ surf_index, surf_offset);
+
+ isl_surf_fill_state(&brw->isl_dev, dw, .surf = &surf, .view = view,
+ .address = mt->bo->offset64 + mt->offset,
+ .aux_surf = aux_surf, .aux_usage = aux_usage,
+ .aux_address = aux_offset,
+ .mocs = mocs, .clear_color = clear_color);
+
+ drm_intel_bo_emit_reloc(brw->batch.bo,
+ *surf_offset + 4 * ss_info.reloc_dw,
+ mt->bo, mt->offset,
+ read_domains, write_domains);
+
+ if (aux_surf) {
+ /* On gen7 and prior, the upper 20 bits of surface state DWORD 6 are the
+ * upper 20 bits of the GPU address of the MCS buffer; the lower 12 bits
+ * contain other control information. Since buffer addresses are always
+ * on 4k boundaries (and thus have their lower 12 bits zero), we can use
+ * an ordinary reloc to do the necessary address translation.
+ */
+ assert((aux_offset & 0xfff) == 0);
+ drm_intel_bo_emit_reloc(brw->batch.bo,
+ *surf_offset + 4 * ss_info.aux_reloc_dw,
+ mt->mcs_mt->bo, dw[ss_info.aux_reloc_dw] & 0xfff,
+ read_domains, write_domains);
+ }
+}
+
+uint32_t
+brw_update_renderbuffer_surface(struct brw_context *brw,
+ struct gl_renderbuffer *rb,
+ bool layered, unsigned unit /* unused */,
+ uint32_t surf_index)
+{
+ struct gl_context *ctx = &brw->ctx;
+ struct intel_renderbuffer *irb = intel_renderbuffer(rb);
+ struct intel_mipmap_tree *mt = irb->mt;
+
+ assert(brw_render_target_supported(brw, rb));
+ intel_miptree_used_for_rendering(mt);
+
+ mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
+ if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
+ _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
+ __func__, _mesa_get_format_name(rb_format));
+ }
+
+ const unsigned layer_multiplier =
+ (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
+ irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ?
+ MAX2(irb->mt->num_samples, 1) : 1;
+
+ struct isl_view view = {
+ .format = brw->render_target_format[rb_format],
+ .base_level = irb->mt_level - irb->mt->first_level,
+ .levels = 1,
+ .base_array_layer = irb->mt_layer / layer_multiplier,
+ .array_len = MAX2(irb->layer_count, 1),
+ .channel_select = {
+ ISL_CHANNEL_SELECT_RED,
+ ISL_CHANNEL_SELECT_GREEN,
+ ISL_CHANNEL_SELECT_BLUE,
+ ISL_CHANNEL_SELECT_ALPHA,
+ },
+ .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT,
+ };
+
+ uint32_t offset;
+ brw_emit_surface_state(brw, mt, &view,
+ surface_state_infos[brw->gen].rb_mocs, false,
+ &offset, surf_index,
+ I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER);
+ return offset;
+}
+
GLuint
translate_tex_target(GLenum target)
{
return BRW_SURFACE_MULTISAMPLECOUNT_1;
}
-void
-brw_configure_w_tiled(const struct intel_mipmap_tree *mt,
- bool is_render_target,
- unsigned *width, unsigned *height,
- unsigned *pitch, uint32_t *tiling, unsigned *format)
-{
- static const unsigned halign_stencil = 8;
-
- /* In Y-tiling row is twice as wide as in W-tiling, and subsequently
- * there are half as many rows.
- * In addition, mip-levels are accessed manually by the program and
- * therefore the surface is setup to cover all the mip-levels for one slice.
- * (Hardware is still used to access individual slices).
- */
- *tiling = I915_TILING_Y;
- *pitch = mt->pitch * 2;
- *width = ALIGN(mt->total_width, halign_stencil) * 2;
- *height = (mt->total_height / mt->physical_depth0) / 2;
-
- if (is_render_target) {
- *format = BRW_SURFACEFORMAT_R8_UINT;
- }
-}
-
-
/**
* Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
* swizzling.
}
}
+ GLenum datatype = _mesa_get_format_datatype(img->TexFormat);
+
/* If the texture's format is alpha-only, force R, G, and B to
* 0.0. Similarly, if the texture's format has no alpha channel,
* force the alpha value read to 1.0. This allows for the
swizzles[1] = SWIZZLE_ZERO;
swizzles[2] = SWIZZLE_ZERO;
break;
+ case GL_LUMINANCE:
+ if (t->_IsIntegerFormat || datatype == GL_SIGNED_NORMALIZED) {
+ swizzles[0] = SWIZZLE_X;
+ swizzles[1] = SWIZZLE_X;
+ swizzles[2] = SWIZZLE_X;
+ swizzles[3] = SWIZZLE_ONE;
+ }
+ break;
+ case GL_LUMINANCE_ALPHA:
+ if (datatype == GL_SIGNED_NORMALIZED) {
+ swizzles[0] = SWIZZLE_X;
+ swizzles[1] = SWIZZLE_X;
+ swizzles[2] = SWIZZLE_X;
+ swizzles[3] = SWIZZLE_W;
+ }
+ break;
+ case GL_INTENSITY:
+ if (datatype == GL_SIGNED_NORMALIZED) {
+ swizzles[0] = SWIZZLE_X;
+ swizzles[1] = SWIZZLE_X;
+ swizzles[2] = SWIZZLE_X;
+ swizzles[3] = SWIZZLE_X;
+ }
+ break;
case GL_RED:
case GL_RG:
case GL_RGB:
swizzles[GET_SWZ(t->_Swizzle, 3)]);
}
+/**
+ * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
+ * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
+ *
+ * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
+ * 0 1 2 3 4 5
+ * 4 5 6 7 0 1
+ * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
+ *
+ * which is simply adding 4 then modding by 8 (or anding with 7).
+ *
+ * We then may need to apply workarounds for textureGather hardware bugs.
+ */
+static unsigned
+swizzle_to_scs(GLenum swizzle, bool need_green_to_blue)
+{
+ unsigned scs = (swizzle + 4) & 7;
+
+ return (need_green_to_blue && scs == HSW_SCS_GREEN) ? HSW_SCS_BLUE : scs;
+}
+
+void
+brw_update_texture_surface(struct gl_context *ctx,
+ unsigned unit,
+ uint32_t *surf_offset,
+ bool for_gather,
+ uint32_t plane)
+{
+ struct brw_context *brw = brw_context(ctx);
+ struct gl_texture_object *obj = ctx->Texture.Unit[unit]._Current;
+
+ if (obj->Target == GL_TEXTURE_BUFFER) {
+ brw_update_buffer_texture_surface(ctx, unit, surf_offset);
+
+ } else {
+ struct intel_texture_object *intel_obj = intel_texture_object(obj);
+ struct intel_mipmap_tree *mt = intel_obj->mt;
+ struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
+ /* If this is a view with restricted NumLayers, then our effective depth
+ * is not just the miptree depth.
+ */
+ const unsigned mt_num_layers =
+ mt->logical_depth0 * (_mesa_is_cube_map_texture(mt->target) ? 6 : 1);
+ const unsigned view_num_layers =
+ (obj->Immutable && obj->Target != GL_TEXTURE_3D) ? obj->NumLayers :
+ mt_num_layers;
+
+ /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
+ * texturing functions that return a float, as our code generation always
+ * selects the .x channel (which would always be 0).
+ */
+ struct gl_texture_image *firstImage = obj->Image[0][obj->BaseLevel];
+ const bool alpha_depth = obj->DepthMode == GL_ALPHA &&
+ (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
+ firstImage->_BaseFormat == GL_DEPTH_STENCIL);
+ const unsigned swizzle = (unlikely(alpha_depth) ? SWIZZLE_XYZW :
+ brw_get_texture_swizzle(&brw->ctx, obj));
+
+ unsigned format = translate_tex_format(
+ brw, intel_obj->_Format, sampler->sRGBDecode);
+
+ /* Implement gen6 and gen7 gather work-around */
+ bool need_green_to_blue = false;
+ if (for_gather) {
+ if (brw->gen == 7 && format == BRW_SURFACEFORMAT_R32G32_FLOAT) {
+ format = BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
+ need_green_to_blue = brw->is_haswell;
+ } else if (brw->gen == 6) {
+ /* Sandybridge's gather4 message is broken for integer formats.
+ * To work around this, we pretend the surface is UNORM for
+ * 8 or 16-bit formats, and emit shader instructions to recover
+ * the real INT/UINT value. For 32-bit formats, we pretend
+ * the surface is FLOAT, and simply reinterpret the resulting
+ * bits.
+ */
+ switch (format) {
+ case BRW_SURFACEFORMAT_R8_SINT:
+ case BRW_SURFACEFORMAT_R8_UINT:
+ format = BRW_SURFACEFORMAT_R8_UNORM;
+ break;
+
+ case BRW_SURFACEFORMAT_R16_SINT:
+ case BRW_SURFACEFORMAT_R16_UINT:
+ format = BRW_SURFACEFORMAT_R16_UNORM;
+ break;
+
+ case BRW_SURFACEFORMAT_R32_SINT:
+ case BRW_SURFACEFORMAT_R32_UINT:
+ format = BRW_SURFACEFORMAT_R32_FLOAT;
+ break;
+
+ default:
+ break;
+ }
+ }
+ }
+
+ if (obj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) {
+ assert(brw->gen >= 8);
+ mt = mt->stencil_mt;
+ format = BRW_SURFACEFORMAT_R8_UINT;
+ } else if (obj->Target == GL_TEXTURE_EXTERNAL_OES) {
+ if (plane > 0)
+ mt = mt->plane[plane - 1];
+ if (mt == NULL)
+ return;
+ format = translate_tex_format(brw, mt->format, sampler->sRGBDecode);
+ }
+
+ const int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
+
+ struct isl_view view = {
+ .format = format,
+ .base_level = obj->MinLevel + obj->BaseLevel,
+ .levels = intel_obj->_MaxLevel - obj->BaseLevel + 1,
+ .base_array_layer = obj->MinLayer,
+ .array_len = view_num_layers,
+ .channel_select = {
+ swizzle_to_scs(GET_SWZ(swizzle, 0), need_green_to_blue),
+ swizzle_to_scs(GET_SWZ(swizzle, 1), need_green_to_blue),
+ swizzle_to_scs(GET_SWZ(swizzle, 2), need_green_to_blue),
+ swizzle_to_scs(GET_SWZ(swizzle, 3), need_green_to_blue),
+ },
+ .usage = ISL_SURF_USAGE_TEXTURE_BIT,
+ };
+
+ if (obj->Target == GL_TEXTURE_CUBE_MAP ||
+ obj->Target == GL_TEXTURE_CUBE_MAP_ARRAY)
+ view.usage |= ISL_SURF_USAGE_CUBE_BIT;
+
+ brw_emit_surface_state(brw, mt, &view,
+ surface_state_infos[brw->gen].tex_mocs, for_gather,
+ surf_offset, surf_index,
+ I915_GEM_DOMAIN_SAMPLER, 0);
+ }
+}
+
static void
gen4_emit_buffer_surface_state(struct brw_context *brw,
uint32_t *out_offset,
unsigned surface_format,
unsigned buffer_size,
unsigned pitch,
- unsigned mocs,
bool rw)
{
+ unsigned elements = buffer_size / pitch;
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
6 * 4, 32, out_offset);
memset(surf, 0, 6 * 4);
surface_format << BRW_SURFACE_FORMAT_SHIFT |
(brw->gen >= 6 ? BRW_SURFACE_RC_READ_WRITE : 0);
surf[1] = (bo ? bo->offset64 : 0) + buffer_offset; /* reloc */
- surf[2] = (buffer_size & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
- ((buffer_size >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT;
- surf[3] = ((buffer_size >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
+ surf[2] = ((elements - 1) & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
+ (((elements - 1) >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT;
+ surf[3] = (((elements - 1) >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
(pitch - 1) << BRW_SURFACE_PITCH_SHIFT;
/* Emit relocation to surface contents. The 965 PRM, Volume 4, section
brw->vtbl.emit_buffer_surface_state(brw, surf_offset, bo,
tObj->BufferOffset,
brw_format,
- size / texel_size,
+ size,
texel_size,
- 0, /* mocs */
false /* rw */);
}
-static void
-brw_update_texture_surface(struct gl_context *ctx,
- unsigned unit,
- uint32_t *surf_offset,
- bool for_gather)
-{
- struct brw_context *brw = brw_context(ctx);
- struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
- struct intel_texture_object *intelObj = intel_texture_object(tObj);
- struct intel_mipmap_tree *mt = intelObj->mt;
- struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
- uint32_t *surf;
-
- /* BRW_NEW_TEXTURE_BUFFER */
- if (tObj->Target == GL_TEXTURE_BUFFER) {
- brw_update_buffer_texture_surface(ctx, unit, surf_offset);
- return;
- }
-
- surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 6 * 4, 32, surf_offset);
-
- uint32_t tex_format = translate_tex_format(brw, mt->format,
- sampler->sRGBDecode);
-
- if (for_gather) {
- /* Sandybridge's gather4 message is broken for integer formats.
- * To work around this, we pretend the surface is UNORM for
- * 8 or 16-bit formats, and emit shader instructions to recover
- * the real INT/UINT value. For 32-bit formats, we pretend
- * the surface is FLOAT, and simply reinterpret the resulting
- * bits.
- */
- switch (tex_format) {
- case BRW_SURFACEFORMAT_R8_SINT:
- case BRW_SURFACEFORMAT_R8_UINT:
- tex_format = BRW_SURFACEFORMAT_R8_UNORM;
- break;
-
- case BRW_SURFACEFORMAT_R16_SINT:
- case BRW_SURFACEFORMAT_R16_UINT:
- tex_format = BRW_SURFACEFORMAT_R16_UNORM;
- break;
-
- case BRW_SURFACEFORMAT_R32_SINT:
- case BRW_SURFACEFORMAT_R32_UINT:
- tex_format = BRW_SURFACEFORMAT_R32_FLOAT;
- break;
-
- default:
- break;
- }
- }
-
- surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
- BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
- BRW_SURFACE_CUBEFACE_ENABLES |
- tex_format << BRW_SURFACE_FORMAT_SHIFT);
-
- surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
-
- surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
- (mt->logical_width0 - 1) << BRW_SURFACE_WIDTH_SHIFT |
- (mt->logical_height0 - 1) << BRW_SURFACE_HEIGHT_SHIFT);
-
- surf[3] = (brw_get_surface_tiling_bits(mt->tiling) |
- (mt->logical_depth0 - 1) << BRW_SURFACE_DEPTH_SHIFT |
- (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
-
- surf[4] = (brw_get_surface_num_multisamples(mt->num_samples) |
- SET_FIELD(tObj->BaseLevel - mt->first_level, BRW_SURFACE_MIN_LOD));
-
- surf[5] = mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
-
- /* Emit relocation to surface contents */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- I915_GEM_DOMAIN_SAMPLER, 0);
-}
-
/**
* Create the constant buffer surface. Vertex/fragment shader constants will be
* read from this buffer with Data Port Read instructions/messages.
drm_intel_bo *bo,
uint32_t offset,
uint32_t size,
- uint32_t *out_offset,
- bool dword_pitch)
+ uint32_t *out_offset)
{
- uint32_t stride = dword_pitch ? 4 : 16;
- uint32_t elements = ALIGN(size, stride) / stride;
-
brw->vtbl.emit_buffer_surface_state(brw, out_offset, bo, offset,
BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
- elements, stride, 0, false);
+ size, 1, false);
+}
+
+/**
+ * Create the buffer surface. Shader buffer variables will be
+ * read from / write to this buffer with Data Port Read/Write
+ * instructions/messages.
+ */
+void
+brw_create_buffer_surface(struct brw_context *brw,
+ drm_intel_bo *bo,
+ uint32_t offset,
+ uint32_t size,
+ uint32_t *out_offset)
+{
+ /* Use a raw surface so we can reuse existing untyped read/write/atomic
+ * messages. We need these specifically for the fragment shader since they
+ * include a pixel mask header that we need to ensure correct behavior
+ * with helper invocations, which cannot write to the buffer.
+ */
+ brw->vtbl.emit_buffer_surface_state(brw, out_offset, bo, offset,
+ BRW_SURFACEFORMAT_RAW,
+ size, 1, true);
}
/**
/* _NEW_PROGRAM_CONSTANTS */
brw_upload_pull_constants(brw, BRW_NEW_SURFACES, &fp->program.Base,
- stage_state, prog_data, true);
+ stage_state, prog_data);
}
const struct brw_tracked_state brw_wm_pull_constants = {
.dirty = {
.mesa = _NEW_PROGRAM_CONSTANTS,
.brw = BRW_NEW_BATCH |
+ BRW_NEW_BLORP |
BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_FS_PROG_DATA,
},
* hardware discard the target 0 color output..
*/
static void
-brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
+brw_emit_null_surface_state(struct brw_context *brw,
+ unsigned width,
+ unsigned height,
+ unsigned samples,
+ uint32_t *out_offset)
{
/* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
* Notes):
*
* - Surface Format must be R8G8B8A8_UNORM.
*/
- struct gl_context *ctx = &brw->ctx;
- uint32_t *surf;
unsigned surface_type = BRW_SURFACE_NULL;
drm_intel_bo *bo = NULL;
unsigned pitch_minus_1 = 0;
uint32_t multisampling_state = 0;
- uint32_t surf_index =
- brw->wm.prog_data->binding_table.render_target_start + unit;
-
- /* _NEW_BUFFERS */
- const struct gl_framebuffer *fb = ctx->DrawBuffer;
-
- surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
- &brw->wm.base.surf_offset[surf_index]);
+ uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
+ out_offset);
- if (fb->Visual.samples > 1) {
+ if (samples > 1) {
/* On Gen6, null render targets seem to cause GPU hangs when
* multisampling. So work around this problem by rendering into dummy
* color buffer.
* width_in_tiles and height_in_tiles by dividing the width and height
* by 16 rather than the normal Y-tile size of 32.
*/
- unsigned width_in_tiles = ALIGN(fb->Width, 16) / 16;
- unsigned height_in_tiles = ALIGN(fb->Height, 16) / 16;
+ unsigned width_in_tiles = ALIGN(width, 16) / 16;
+ unsigned height_in_tiles = ALIGN(height, 16) / 16;
unsigned size_needed = (width_in_tiles + height_in_tiles - 1) * 4096;
brw_get_scratch_bo(brw, &brw->wm.multisampled_null_render_target_bo,
size_needed);
bo = brw->wm.multisampled_null_render_target_bo;
surface_type = BRW_SURFACE_2D;
pitch_minus_1 = 127;
- multisampling_state =
- brw_get_surface_num_multisamples(fb->Visual.samples);
+ multisampling_state = brw_get_surface_num_multisamples(samples);
}
surf[0] = (surface_type << BRW_SURFACE_TYPE_SHIFT |
1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
}
surf[1] = bo ? bo->offset64 : 0;
- surf[2] = ((fb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
- (fb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
+ surf[2] = ((width - 1) << BRW_SURFACE_WIDTH_SHIFT |
+ (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
/* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
* Notes):
if (bo) {
drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.base.surf_offset[surf_index] + 4,
+ *out_offset + 4,
bo, 0,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
}
* While it is only used for the front/back buffer currently, it should be
* usable for further buffers when doing ARB_draw_buffer support.
*/
-static void
-brw_update_renderbuffer_surface(struct brw_context *brw,
- struct gl_renderbuffer *rb,
- bool layered,
- unsigned int unit)
+static uint32_t
+gen4_update_renderbuffer_surface(struct brw_context *brw,
+ struct gl_renderbuffer *rb,
+ bool layered, unsigned unit,
+ uint32_t surf_index)
{
struct gl_context *ctx = &brw->ctx;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
uint32_t *surf;
uint32_t tile_x, tile_y;
uint32_t format = 0;
+ uint32_t offset;
/* _NEW_BUFFERS */
mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
- uint32_t surf_index =
- brw->wm.prog_data->binding_table.render_target_start + unit;
+ /* BRW_NEW_FS_PROG_DATA */
assert(!layered);
intel_miptree_used_for_rendering(irb->mt);
- surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
- &brw->wm.base.surf_offset[surf_index]);
+ surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, &offset);
format = brw->render_target_format[rb_format];
if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
_mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
- __FUNCTION__, _mesa_get_format_name(rb_format));
+ __func__, _mesa_get_format_name(rb_format));
}
surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
format << BRW_SURFACE_FORMAT_SHIFT);
/* reloc */
+ assert(mt->offset % mt->cpp == 0);
surf[1] = (intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) +
- mt->bo->offset64);
+ mt->bo->offset64 + mt->offset);
surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
assert(tile_y % 2 == 0);
surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
(tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
- (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
+ (mt->valign == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
if (brw->gen < 6) {
/* _NEW_COLOR */
}
drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.base.surf_offset[surf_index] + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
+ offset + 4,
+ mt->bo,
+ surf[1] - mt->bo->offset64,
+ I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER);
+
+ return offset;
}
/**
* Construct SURFACE_STATE objects for renderbuffers/draw buffers.
*/
-static void
-brw_update_renderbuffer_surfaces(struct brw_context *brw)
+void
+brw_update_renderbuffer_surfaces(struct brw_context *brw,
+ const struct gl_framebuffer *fb,
+ uint32_t render_target_start,
+ uint32_t *surf_offset)
{
- struct gl_context *ctx = &brw->ctx;
GLuint i;
+ const unsigned int w = _mesa_geometric_width(fb);
+ const unsigned int h = _mesa_geometric_height(fb);
+ const unsigned int s = _mesa_geometric_samples(fb);
- /* _NEW_BUFFERS | _NEW_COLOR */
/* Update surfaces for drawing buffers */
- if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
- for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
- if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
- brw->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i],
- ctx->DrawBuffer->MaxNumLayers > 0, i);
+ if (fb->_NumColorDrawBuffers >= 1) {
+ for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
+ const uint32_t surf_index = render_target_start + i;
+
+ if (intel_renderbuffer(fb->_ColorDrawBuffers[i])) {
+ surf_offset[surf_index] =
+ brw->vtbl.update_renderbuffer_surface(
+ brw, fb->_ColorDrawBuffers[i],
+ _mesa_geometric_layers(fb) > 0, i, surf_index);
} else {
- brw->vtbl.update_null_renderbuffer_surface(brw, i);
+ brw->vtbl.emit_null_surface_state(brw, w, h, s,
+ &surf_offset[surf_index]);
}
}
} else {
- brw->vtbl.update_null_renderbuffer_surface(brw, 0);
+ const uint32_t surf_index = render_target_start;
+ brw->vtbl.emit_null_surface_state(brw, w, h, s,
+ &surf_offset[surf_index]);
}
- brw->state.dirty.brw |= BRW_NEW_SURFACES;
+}
+
+static void
+update_renderbuffer_surfaces(struct brw_context *brw)
+{
+ const struct gl_context *ctx = &brw->ctx;
+
+ /* _NEW_BUFFERS | _NEW_COLOR */
+ const struct gl_framebuffer *fb = ctx->DrawBuffer;
+ brw_update_renderbuffer_surfaces(
+ brw, fb,
+ brw->wm.prog_data->binding_table.render_target_start,
+ brw->wm.base.surf_offset);
+ brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
}
const struct brw_tracked_state brw_renderbuffer_surfaces = {
.dirty = {
.mesa = _NEW_BUFFERS |
_NEW_COLOR,
- .brw = BRW_NEW_BATCH,
+ .brw = BRW_NEW_BATCH |
+ BRW_NEW_BLORP |
+ BRW_NEW_FS_PROG_DATA,
},
- .emit = brw_update_renderbuffer_surfaces,
+ .emit = update_renderbuffer_surfaces,
};
const struct brw_tracked_state gen6_renderbuffer_surfaces = {
.dirty = {
.mesa = _NEW_BUFFERS,
- .brw = BRW_NEW_BATCH,
+ .brw = BRW_NEW_BATCH |
+ BRW_NEW_BLORP,
},
- .emit = brw_update_renderbuffer_surfaces,
+ .emit = update_renderbuffer_surfaces,
};
update_stage_texture_surfaces(struct brw_context *brw,
const struct gl_program *prog,
struct brw_stage_state *stage_state,
- bool for_gather)
+ bool for_gather, uint32_t plane)
{
if (!prog)
return;
struct gl_context *ctx = &brw->ctx;
uint32_t *surf_offset = stage_state->surf_offset;
+
+ /* BRW_NEW_*_PROG_DATA */
if (for_gather)
surf_offset += stage_state->prog_data->binding_table.gather_texture_start;
else
- surf_offset += stage_state->prog_data->binding_table.texture_start;
+ surf_offset += stage_state->prog_data->binding_table.plane_start[plane];
unsigned num_samplers = _mesa_fls(prog->SamplersUsed);
for (unsigned s = 0; s < num_samplers; s++) {
/* _NEW_TEXTURE */
if (ctx->Texture.Unit[unit]._Current) {
- brw->vtbl.update_texture_surface(ctx, unit, surf_offset + s, for_gather);
+ brw->vtbl.update_texture_surface(ctx, unit, surf_offset + s, for_gather, plane);
}
}
}
/* BRW_NEW_VERTEX_PROGRAM */
struct gl_program *vs = (struct gl_program *) brw->vertex_program;
+ /* BRW_NEW_TESS_PROGRAMS */
+ struct gl_program *tcs = (struct gl_program *) brw->tess_ctrl_program;
+ struct gl_program *tes = (struct gl_program *) brw->tess_eval_program;
+
/* BRW_NEW_GEOMETRY_PROGRAM */
struct gl_program *gs = (struct gl_program *) brw->geometry_program;
struct gl_program *fs = (struct gl_program *) brw->fragment_program;
/* _NEW_TEXTURE */
- update_stage_texture_surfaces(brw, vs, &brw->vs.base, false);
- update_stage_texture_surfaces(brw, gs, &brw->gs.base, false);
- update_stage_texture_surfaces(brw, fs, &brw->wm.base, false);
+ update_stage_texture_surfaces(brw, vs, &brw->vs.base, false, 0);
+ update_stage_texture_surfaces(brw, tcs, &brw->tcs.base, false, 0);
+ update_stage_texture_surfaces(brw, tes, &brw->tes.base, false, 0);
+ update_stage_texture_surfaces(brw, gs, &brw->gs.base, false, 0);
+ update_stage_texture_surfaces(brw, fs, &brw->wm.base, false, 0);
/* emit alternate set of surface state for gather. this
* allows the surface format to be overriden for only the
* gather4 messages. */
if (brw->gen < 8) {
if (vs && vs->UsesGather)
- update_stage_texture_surfaces(brw, vs, &brw->vs.base, true);
+ update_stage_texture_surfaces(brw, vs, &brw->vs.base, true, 0);
+ if (tcs && tcs->UsesGather)
+ update_stage_texture_surfaces(brw, tcs, &brw->tcs.base, true, 0);
+ if (tes && tes->UsesGather)
+ update_stage_texture_surfaces(brw, tes, &brw->tes.base, true, 0);
if (gs && gs->UsesGather)
- update_stage_texture_surfaces(brw, gs, &brw->gs.base, true);
+ update_stage_texture_surfaces(brw, gs, &brw->gs.base, true, 0);
if (fs && fs->UsesGather)
- update_stage_texture_surfaces(brw, fs, &brw->wm.base, true);
+ update_stage_texture_surfaces(brw, fs, &brw->wm.base, true, 0);
+ }
+
+ if (fs) {
+ update_stage_texture_surfaces(brw, fs, &brw->wm.base, false, 1);
+ update_stage_texture_surfaces(brw, fs, &brw->wm.base, false, 2);
}
- brw->state.dirty.brw |= BRW_NEW_SURFACES;
+ brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
}
const struct brw_tracked_state brw_texture_surfaces = {
.dirty = {
.mesa = _NEW_TEXTURE,
.brw = BRW_NEW_BATCH |
+ BRW_NEW_BLORP |
BRW_NEW_FRAGMENT_PROGRAM |
+ BRW_NEW_FS_PROG_DATA |
BRW_NEW_GEOMETRY_PROGRAM |
+ BRW_NEW_GS_PROG_DATA |
+ BRW_NEW_TESS_PROGRAMS |
+ BRW_NEW_TCS_PROG_DATA |
+ BRW_NEW_TES_PROG_DATA |
BRW_NEW_TEXTURE_BUFFER |
- BRW_NEW_VERTEX_PROGRAM,
+ BRW_NEW_VERTEX_PROGRAM |
+ BRW_NEW_VS_PROG_DATA,
},
.emit = brw_update_texture_surfaces,
};
+static void
+brw_update_cs_texture_surfaces(struct brw_context *brw)
+{
+ /* BRW_NEW_COMPUTE_PROGRAM */
+ struct gl_program *cs = (struct gl_program *) brw->compute_program;
+
+ /* _NEW_TEXTURE */
+ update_stage_texture_surfaces(brw, cs, &brw->cs.base, false, 0);
+
+ /* emit alternate set of surface state for gather. this
+ * allows the surface format to be overriden for only the
+ * gather4 messages.
+ */
+ if (brw->gen < 8) {
+ if (cs && cs->UsesGather)
+ update_stage_texture_surfaces(brw, cs, &brw->cs.base, true, 0);
+ }
+
+ brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
+}
+
+const struct brw_tracked_state brw_cs_texture_surfaces = {
+ .dirty = {
+ .mesa = _NEW_TEXTURE,
+ .brw = BRW_NEW_BATCH |
+ BRW_NEW_BLORP |
+ BRW_NEW_COMPUTE_PROGRAM,
+ },
+ .emit = brw_update_cs_texture_surfaces,
+};
+
+
void
brw_upload_ubo_surfaces(struct brw_context *brw,
- struct gl_shader *shader,
+ struct gl_linked_shader *shader,
struct brw_stage_state *stage_state,
struct brw_stage_prog_data *prog_data)
{
if (!shader)
return;
- uint32_t *surf_offsets =
+ uint32_t *ubo_surf_offsets =
&stage_state->surf_offset[prog_data->binding_table.ubo_start];
for (int i = 0; i < shader->NumUniformBlocks; i++) {
- struct gl_uniform_buffer_binding *binding;
- struct intel_buffer_object *intel_bo;
-
- binding = &ctx->UniformBufferBindings[shader->UniformBlocks[i].Binding];
- intel_bo = intel_buffer_object(binding->BufferObject);
- drm_intel_bo *bo =
- intel_bufferobj_buffer(brw, intel_bo,
- binding->Offset,
- binding->BufferObject->Size - binding->Offset);
-
- /* Because behavior for referencing outside of the binding's size in the
- * glBindBufferRange case is undefined, we can just bind the whole buffer
- * glBindBufferBase wants and be a correct implementation.
- */
- brw_create_constant_surface(brw, bo, binding->Offset,
- bo->size - binding->Offset,
- &surf_offsets[i],
- shader->Stage == MESA_SHADER_FRAGMENT);
+ struct gl_uniform_buffer_binding *binding =
+ &ctx->UniformBufferBindings[shader->UniformBlocks[i]->Binding];
+
+ if (binding->BufferObject == ctx->Shared->NullBufferObj) {
+ brw->vtbl.emit_null_surface_state(brw, 1, 1, 1, &ubo_surf_offsets[i]);
+ } else {
+ struct intel_buffer_object *intel_bo =
+ intel_buffer_object(binding->BufferObject);
+ GLsizeiptr size = binding->BufferObject->Size - binding->Offset;
+ if (!binding->AutomaticSize)
+ size = MIN2(size, binding->Size);
+ drm_intel_bo *bo =
+ intel_bufferobj_buffer(brw, intel_bo,
+ binding->Offset,
+ size);
+ brw_create_constant_surface(brw, bo, binding->Offset,
+ size,
+ &ubo_surf_offsets[i]);
+ }
+ }
+
+ uint32_t *ssbo_surf_offsets =
+ &stage_state->surf_offset[prog_data->binding_table.ssbo_start];
+
+ for (int i = 0; i < shader->NumShaderStorageBlocks; i++) {
+ struct gl_shader_storage_buffer_binding *binding =
+ &ctx->ShaderStorageBufferBindings[shader->ShaderStorageBlocks[i]->Binding];
+
+ if (binding->BufferObject == ctx->Shared->NullBufferObj) {
+ brw->vtbl.emit_null_surface_state(brw, 1, 1, 1, &ssbo_surf_offsets[i]);
+ } else {
+ struct intel_buffer_object *intel_bo =
+ intel_buffer_object(binding->BufferObject);
+ GLsizeiptr size = binding->BufferObject->Size - binding->Offset;
+ if (!binding->AutomaticSize)
+ size = MIN2(size, binding->Size);
+ drm_intel_bo *bo =
+ intel_bufferobj_buffer(brw, intel_bo,
+ binding->Offset,
+ size);
+ brw_create_buffer_surface(brw, bo, binding->Offset,
+ size,
+ &ssbo_surf_offsets[i]);
+ }
}
- if (shader->NumUniformBlocks)
- brw->state.dirty.brw |= BRW_NEW_SURFACES;
+ if (shader->NumUniformBlocks || shader->NumShaderStorageBlocks)
+ brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
}
static void
.dirty = {
.mesa = _NEW_PROGRAM,
.brw = BRW_NEW_BATCH |
+ BRW_NEW_BLORP |
BRW_NEW_FS_PROG_DATA |
BRW_NEW_UNIFORM_BUFFER,
},
.emit = brw_upload_wm_ubo_surfaces,
};
+static void
+brw_upload_cs_ubo_surfaces(struct brw_context *brw)
+{
+ struct gl_context *ctx = &brw->ctx;
+ /* _NEW_PROGRAM */
+ struct gl_shader_program *prog =
+ ctx->_Shader->CurrentProgram[MESA_SHADER_COMPUTE];
+
+ if (!prog)
+ return;
+
+ /* BRW_NEW_CS_PROG_DATA */
+ brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_COMPUTE],
+ &brw->cs.base, &brw->cs.prog_data->base);
+}
+
+const struct brw_tracked_state brw_cs_ubo_surfaces = {
+ .dirty = {
+ .mesa = _NEW_PROGRAM,
+ .brw = BRW_NEW_BATCH |
+ BRW_NEW_BLORP |
+ BRW_NEW_CS_PROG_DATA |
+ BRW_NEW_UNIFORM_BUFFER,
+ },
+ .emit = brw_upload_cs_ubo_surfaces,
+};
+
void
brw_upload_abo_surfaces(struct brw_context *brw,
- struct gl_shader_program *prog,
+ struct gl_linked_shader *shader,
struct brw_stage_state *stage_state,
struct brw_stage_prog_data *prog_data)
{
uint32_t *surf_offsets =
&stage_state->surf_offset[prog_data->binding_table.abo_start];
- for (int i = 0; i < prog->NumAtomicBuffers; i++) {
- struct gl_atomic_buffer_binding *binding =
- &ctx->AtomicBufferBindings[prog->AtomicBuffers[i].Binding];
- struct intel_buffer_object *intel_bo =
- intel_buffer_object(binding->BufferObject);
- drm_intel_bo *bo = intel_bufferobj_buffer(
- brw, intel_bo, binding->Offset, intel_bo->Base.Size - binding->Offset);
+ if (shader && shader->NumAtomicBuffers) {
+ for (unsigned i = 0; i < shader->NumAtomicBuffers; i++) {
+ struct gl_atomic_buffer_binding *binding =
+ &ctx->AtomicBufferBindings[shader->AtomicBuffers[i]->Binding];
+ struct intel_buffer_object *intel_bo =
+ intel_buffer_object(binding->BufferObject);
+ drm_intel_bo *bo = intel_bufferobj_buffer(
+ brw, intel_bo, binding->Offset, intel_bo->Base.Size - binding->Offset);
+
+ brw->vtbl.emit_buffer_surface_state(brw, &surf_offsets[i], bo,
+ binding->Offset, BRW_SURFACEFORMAT_RAW,
+ bo->size - binding->Offset, 1, true);
+ }
- brw->vtbl.create_raw_surface(brw, bo, binding->Offset,
- bo->size - binding->Offset,
- &surf_offsets[i], true);
+ brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
}
-
- if (prog->NumAtomicBuffers)
- brw->state.dirty.brw |= BRW_NEW_SURFACES;
}
static void
{
struct gl_context *ctx = &brw->ctx;
/* _NEW_PROGRAM */
- struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram;
+ struct gl_shader_program *prog = ctx->_Shader->_CurrentFragmentProgram;
if (prog) {
/* BRW_NEW_FS_PROG_DATA */
- brw_upload_abo_surfaces(brw, prog, &brw->wm.base,
- &brw->wm.prog_data->base);
+ brw_upload_abo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
+ &brw->wm.base, &brw->wm.prog_data->base);
}
}
.dirty = {
.mesa = _NEW_PROGRAM,
.brw = BRW_NEW_ATOMIC_BUFFER |
+ BRW_NEW_BLORP |
BRW_NEW_BATCH |
BRW_NEW_FS_PROG_DATA,
},
.emit = brw_upload_wm_abo_surfaces,
};
+static void
+brw_upload_cs_abo_surfaces(struct brw_context *brw)
+{
+ struct gl_context *ctx = &brw->ctx;
+ /* _NEW_PROGRAM */
+ struct gl_shader_program *prog =
+ ctx->_Shader->CurrentProgram[MESA_SHADER_COMPUTE];
+
+ if (prog) {
+ /* BRW_NEW_CS_PROG_DATA */
+ brw_upload_abo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_COMPUTE],
+ &brw->cs.base, &brw->cs.prog_data->base);
+ }
+}
+
+const struct brw_tracked_state brw_cs_abo_surfaces = {
+ .dirty = {
+ .mesa = _NEW_PROGRAM,
+ .brw = BRW_NEW_ATOMIC_BUFFER |
+ BRW_NEW_BLORP |
+ BRW_NEW_BATCH |
+ BRW_NEW_CS_PROG_DATA,
+ },
+ .emit = brw_upload_cs_abo_surfaces,
+};
+
+static void
+brw_upload_cs_image_surfaces(struct brw_context *brw)
+{
+ struct gl_context *ctx = &brw->ctx;
+ /* _NEW_PROGRAM */
+ struct gl_shader_program *prog =
+ ctx->_Shader->CurrentProgram[MESA_SHADER_COMPUTE];
+
+ if (prog) {
+ /* BRW_NEW_CS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
+ brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_COMPUTE],
+ &brw->cs.base, &brw->cs.prog_data->base);
+ }
+}
+
+const struct brw_tracked_state brw_cs_image_surfaces = {
+ .dirty = {
+ .mesa = _NEW_TEXTURE | _NEW_PROGRAM,
+ .brw = BRW_NEW_BATCH |
+ BRW_NEW_BLORP |
+ BRW_NEW_CS_PROG_DATA |
+ BRW_NEW_IMAGE_UNITS
+ },
+ .emit = brw_upload_cs_image_surfaces,
+};
+
+static uint32_t
+get_image_format(struct brw_context *brw, mesa_format format, GLenum access)
+{
+ const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
+ uint32_t hw_format = brw_format_for_mesa_format(format);
+ if (access == GL_WRITE_ONLY) {
+ return hw_format;
+ } else if (isl_has_matching_typed_storage_image_format(devinfo, hw_format)) {
+ /* Typed surface reads support a very limited subset of the shader
+ * image formats. Translate it into the closest format the
+ * hardware supports.
+ */
+ return isl_lower_storage_image_format(devinfo, hw_format);
+ } else {
+ /* The hardware doesn't actually support a typed format that we can use
+ * so we have to fall back to untyped read/write messages.
+ */
+ return BRW_SURFACEFORMAT_RAW;
+ }
+}
+
+static void
+update_default_image_param(struct brw_context *brw,
+ struct gl_image_unit *u,
+ unsigned surface_idx,
+ struct brw_image_param *param)
+{
+ memset(param, 0, sizeof(*param));
+ param->surface_idx = surface_idx;
+ /* Set the swizzling shifts to all-ones to effectively disable swizzling --
+ * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
+ * detailed explanation of these parameters.
+ */
+ param->swizzling[0] = 0xff;
+ param->swizzling[1] = 0xff;
+}
+
+static void
+update_buffer_image_param(struct brw_context *brw,
+ struct gl_image_unit *u,
+ unsigned surface_idx,
+ struct brw_image_param *param)
+{
+ struct gl_buffer_object *obj = u->TexObj->BufferObject;
+
+ update_default_image_param(brw, u, surface_idx, param);
+
+ param->size[0] = obj->Size / _mesa_get_format_bytes(u->_ActualFormat);
+ param->stride[0] = _mesa_get_format_bytes(u->_ActualFormat);
+}
+
+static void
+update_texture_image_param(struct brw_context *brw,
+ struct gl_image_unit *u,
+ unsigned surface_idx,
+ struct brw_image_param *param)
+{
+ struct intel_mipmap_tree *mt = intel_texture_object(u->TexObj)->mt;
+
+ update_default_image_param(brw, u, surface_idx, param);
+
+ param->size[0] = minify(mt->logical_width0, u->Level);
+ param->size[1] = minify(mt->logical_height0, u->Level);
+ param->size[2] = (!u->Layered ? 1 :
+ u->TexObj->Target == GL_TEXTURE_CUBE_MAP ? 6 :
+ u->TexObj->Target == GL_TEXTURE_3D ?
+ minify(mt->logical_depth0, u->Level) :
+ mt->logical_depth0);
+
+ intel_miptree_get_image_offset(mt, u->Level, u->_Layer,
+ ¶m->offset[0],
+ ¶m->offset[1]);
+
+ param->stride[0] = mt->cpp;
+ param->stride[1] = mt->pitch / mt->cpp;
+ param->stride[2] =
+ brw_miptree_get_horizontal_slice_pitch(brw, mt, u->Level);
+ param->stride[3] =
+ brw_miptree_get_vertical_slice_pitch(brw, mt, u->Level);
+
+ if (mt->tiling == I915_TILING_X) {
+ /* An X tile is a rectangular block of 512x8 bytes. */
+ param->tiling[0] = _mesa_logbase2(512 / mt->cpp);
+ param->tiling[1] = _mesa_logbase2(8);
+
+ if (brw->has_swizzling) {
+ /* Right shifts required to swizzle bits 9 and 10 of the memory
+ * address with bit 6.
+ */
+ param->swizzling[0] = 3;
+ param->swizzling[1] = 4;
+ }
+ } else if (mt->tiling == I915_TILING_Y) {
+ /* The layout of a Y-tiled surface in memory isn't really fundamentally
+ * different to the layout of an X-tiled surface, we simply pretend that
+ * the surface is broken up in a number of smaller 16Bx32 tiles, each
+ * one arranged in X-major order just like is the case for X-tiling.
+ */
+ param->tiling[0] = _mesa_logbase2(16 / mt->cpp);
+ param->tiling[1] = _mesa_logbase2(32);
+
+ if (brw->has_swizzling) {
+ /* Right shift required to swizzle bit 9 of the memory address with
+ * bit 6.
+ */
+ param->swizzling[0] = 3;
+ }
+ }
+
+ /* 3D textures are arranged in 2D in memory with 2^lod slices per row. The
+ * address calculation algorithm (emit_address_calculation() in
+ * brw_fs_surface_builder.cpp) handles this as a sort of tiling with
+ * modulus equal to the LOD.
+ */
+ param->tiling[2] = (u->TexObj->Target == GL_TEXTURE_3D ? u->Level :
+ 0);
+}
+
+static void
+update_image_surface(struct brw_context *brw,
+ struct gl_image_unit *u,
+ GLenum access,
+ unsigned surface_idx,
+ uint32_t *surf_offset,
+ struct brw_image_param *param)
+{
+ if (_mesa_is_image_unit_valid(&brw->ctx, u)) {
+ struct gl_texture_object *obj = u->TexObj;
+ const unsigned format = get_image_format(brw, u->_ActualFormat, access);
+
+ if (obj->Target == GL_TEXTURE_BUFFER) {
+ struct intel_buffer_object *intel_obj =
+ intel_buffer_object(obj->BufferObject);
+ const unsigned texel_size = (format == BRW_SURFACEFORMAT_RAW ? 1 :
+ _mesa_get_format_bytes(u->_ActualFormat));
+
+ brw->vtbl.emit_buffer_surface_state(
+ brw, surf_offset, intel_obj->buffer, obj->BufferOffset,
+ format, intel_obj->Base.Size, texel_size,
+ access != GL_READ_ONLY);
+
+ update_buffer_image_param(brw, u, surface_idx, param);
+
+ } else {
+ struct intel_texture_object *intel_obj = intel_texture_object(obj);
+ struct intel_mipmap_tree *mt = intel_obj->mt;
+
+ if (format == BRW_SURFACEFORMAT_RAW) {
+ brw->vtbl.emit_buffer_surface_state(
+ brw, surf_offset, mt->bo, mt->offset,
+ format, mt->bo->size - mt->offset, 1 /* pitch */,
+ access != GL_READ_ONLY);
+
+ } else {
+ const unsigned num_layers = (!u->Layered ? 1 :
+ obj->Target == GL_TEXTURE_CUBE_MAP ? 6 :
+ mt->logical_depth0);
+
+ struct isl_view view = {
+ .format = format,
+ .base_level = obj->MinLevel + u->Level,
+ .levels = 1,
+ .base_array_layer = obj->MinLayer + u->_Layer,
+ .array_len = num_layers,
+ .channel_select = {
+ ISL_CHANNEL_SELECT_RED,
+ ISL_CHANNEL_SELECT_GREEN,
+ ISL_CHANNEL_SELECT_BLUE,
+ ISL_CHANNEL_SELECT_ALPHA,
+ },
+ .usage = ISL_SURF_USAGE_STORAGE_BIT,
+ };
+
+ const int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
+
+ brw_emit_surface_state(brw, mt, &view,
+ surface_state_infos[brw->gen].rb_mocs, false,
+ surf_offset, surf_index,
+ I915_GEM_DOMAIN_SAMPLER,
+ access == GL_READ_ONLY ? 0 :
+ I915_GEM_DOMAIN_SAMPLER);
+ }
+
+ update_texture_image_param(brw, u, surface_idx, param);
+ }
+
+ } else {
+ brw->vtbl.emit_null_surface_state(brw, 1, 1, 1, surf_offset);
+ update_default_image_param(brw, u, surface_idx, param);
+ }
+}
+
+void
+brw_upload_image_surfaces(struct brw_context *brw,
+ struct gl_linked_shader *shader,
+ struct brw_stage_state *stage_state,
+ struct brw_stage_prog_data *prog_data)
+{
+ struct gl_context *ctx = &brw->ctx;
+
+ if (shader && shader->NumImages) {
+ for (unsigned i = 0; i < shader->NumImages; i++) {
+ struct gl_image_unit *u = &ctx->ImageUnits[shader->ImageUnits[i]];
+ const unsigned surf_idx = prog_data->binding_table.image_start + i;
+
+ update_image_surface(brw, u, shader->ImageAccess[i],
+ surf_idx,
+ &stage_state->surf_offset[surf_idx],
+ &prog_data->image_param[i]);
+ }
+
+ brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
+ /* This may have changed the image metadata dependent on the context
+ * image unit state and passed to the program as uniforms, make sure
+ * that push and pull constants are reuploaded.
+ */
+ brw->NewGLState |= _NEW_PROGRAM_CONSTANTS;
+ }
+}
+
+static void
+brw_upload_wm_image_surfaces(struct brw_context *brw)
+{
+ struct gl_context *ctx = &brw->ctx;
+ /* BRW_NEW_FRAGMENT_PROGRAM */
+ struct gl_shader_program *prog = ctx->_Shader->_CurrentFragmentProgram;
+
+ if (prog) {
+ /* BRW_NEW_FS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
+ brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
+ &brw->wm.base, &brw->wm.prog_data->base);
+ }
+}
+
+const struct brw_tracked_state brw_wm_image_surfaces = {
+ .dirty = {
+ .mesa = _NEW_TEXTURE,
+ .brw = BRW_NEW_BATCH |
+ BRW_NEW_BLORP |
+ BRW_NEW_FRAGMENT_PROGRAM |
+ BRW_NEW_FS_PROG_DATA |
+ BRW_NEW_IMAGE_UNITS
+ },
+ .emit = brw_upload_wm_image_surfaces,
+};
+
void
gen4_init_vtable_surface_functions(struct brw_context *brw)
{
brw->vtbl.update_texture_surface = brw_update_texture_surface;
- brw->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
- brw->vtbl.update_null_renderbuffer_surface =
- brw_update_null_renderbuffer_surface;
+ brw->vtbl.update_renderbuffer_surface = gen4_update_renderbuffer_surface;
+ brw->vtbl.emit_null_surface_state = brw_emit_null_surface_state;
brw->vtbl.emit_buffer_surface_state = gen4_emit_buffer_surface_state;
}
+
+static void
+brw_upload_cs_work_groups_surface(struct brw_context *brw)
+{
+ struct gl_context *ctx = &brw->ctx;
+ /* _NEW_PROGRAM */
+ struct gl_shader_program *prog =
+ ctx->_Shader->CurrentProgram[MESA_SHADER_COMPUTE];
+
+ if (prog && brw->cs.prog_data->uses_num_work_groups) {
+ const unsigned surf_idx =
+ brw->cs.prog_data->binding_table.work_groups_start;
+ uint32_t *surf_offset = &brw->cs.base.surf_offset[surf_idx];
+ drm_intel_bo *bo;
+ uint32_t bo_offset;
+
+ if (brw->compute.num_work_groups_bo == NULL) {
+ bo = NULL;
+ intel_upload_data(brw,
+ (void *)brw->compute.num_work_groups,
+ 3 * sizeof(GLuint),
+ sizeof(GLuint),
+ &bo,
+ &bo_offset);
+ } else {
+ bo = brw->compute.num_work_groups_bo;
+ bo_offset = brw->compute.num_work_groups_offset;
+ }
+
+ brw->vtbl.emit_buffer_surface_state(brw, surf_offset,
+ bo, bo_offset,
+ BRW_SURFACEFORMAT_RAW,
+ 3 * sizeof(GLuint), 1, true);
+ brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
+ }
+}
+
+const struct brw_tracked_state brw_cs_work_groups_surface = {
+ .dirty = {
+ .brw = BRW_NEW_BLORP |
+ BRW_NEW_CS_WORK_GROUPS
+ },
+ .emit = brw_upload_cs_work_groups_surface,
+};
projects / mesa.git / blobdiff