surf[4] = (brw_get_surface_num_multisamples(mt->num_samples) |
SET_FIELD(tObj->BaseLevel - mt->first_level, BRW_SURFACE_MIN_LOD));
- surf[5] = mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
+ surf[5] = mt->valign == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
/* Emit relocation to surface contents */
drm_intel_bo_emit_reloc(brw->batch.bo,
elements, stride, false);
}
+/**
+ * Create the buffer surface. Shader buffer variables will be
+ * read from / write to this buffer with Data Port Read/Write
+ * instructions/messages.
+ */
+void
+brw_create_buffer_surface(struct brw_context *brw,
+ drm_intel_bo *bo,
+ uint32_t offset,
+ uint32_t size,
+ uint32_t *out_offset,
+ bool dword_pitch)
+{
+ /* Use a raw surface so we can reuse existing untyped read/write/atomic
+ * messages. We need these specifically for the fragment shader since they
+ * include a pixel mask header that we need to ensure correct behavior
+ * with helper invocations, which cannot write to the buffer.
+ */
+ brw->vtbl.emit_buffer_surface_state(brw, out_offset, bo, offset,
+ BRW_SURFACEFORMAT_RAW,
+ size, 1, true);
+}
+
/**
* Set up a binding table entry for use by stream output logic (transform
* feedback).
assert(tile_y % 2 == 0);
surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
(tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
- (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
+ (mt->valign == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
if (brw->gen < 6) {
/* _NEW_COLOR */
/* BRW_NEW_FRAGMENT_PROGRAM */
struct gl_program *fs = (struct gl_program *) brw->fragment_program;
+ /* BRW_NEW_COMPUTE_PROGRAM */
+ struct gl_program *cs = (struct gl_program *) brw->compute_program;
+
/* _NEW_TEXTURE */
update_stage_texture_surfaces(brw, vs, &brw->vs.base, false);
update_stage_texture_surfaces(brw, gs, &brw->gs.base, false);
update_stage_texture_surfaces(brw, fs, &brw->wm.base, false);
+ update_stage_texture_surfaces(brw, cs, &brw->cs.base, false);
/* emit alternate set of surface state for gather. this
* allows the surface format to be overriden for only the
update_stage_texture_surfaces(brw, gs, &brw->gs.base, true);
if (fs && fs->UsesGather)
update_stage_texture_surfaces(brw, fs, &brw->wm.base, true);
+ if (cs && cs->UsesGather)
+ update_stage_texture_surfaces(brw, cs, &brw->cs.base, true);
}
brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
.dirty = {
.mesa = _NEW_TEXTURE,
.brw = BRW_NEW_BATCH |
+ BRW_NEW_COMPUTE_PROGRAM |
BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_FS_PROG_DATA |
BRW_NEW_GEOMETRY_PROGRAM |
&stage_state->surf_offset[prog_data->binding_table.ubo_start];
for (int i = 0; i < shader->NumUniformBlocks; i++) {
- struct gl_uniform_buffer_binding *binding;
struct intel_buffer_object *intel_bo;
- binding = &ctx->UniformBufferBindings[shader->UniformBlocks[i].Binding];
- intel_bo = intel_buffer_object(binding->BufferObject);
- drm_intel_bo *bo =
- intel_bufferobj_buffer(brw, intel_bo,
- binding->Offset,
- binding->BufferObject->Size - binding->Offset);
-
/* Because behavior for referencing outside of the binding's size in the
* glBindBufferRange case is undefined, we can just bind the whole buffer
* glBindBufferBase wants and be a correct implementation.
*/
- brw_create_constant_surface(brw, bo, binding->Offset,
- bo->size - binding->Offset,
- &surf_offsets[i],
- dword_pitch);
+ if (!shader->UniformBlocks[i].IsShaderStorage) {
+ struct gl_uniform_buffer_binding *binding;
+ binding =
+ &ctx->UniformBufferBindings[shader->UniformBlocks[i].Binding];
+ if (binding->BufferObject == ctx->Shared->NullBufferObj) {
+ brw->vtbl.emit_null_surface_state(brw, 1, 1, 1, &surf_offsets[i]);
+ } else {
+ intel_bo = intel_buffer_object(binding->BufferObject);
+ drm_intel_bo *bo =
+ intel_bufferobj_buffer(brw, intel_bo,
+ binding->Offset,
+ binding->BufferObject->Size - binding->Offset);
+ brw_create_constant_surface(brw, bo, binding->Offset,
+ binding->BufferObject->Size - binding->Offset,
+ &surf_offsets[i],
+ dword_pitch);
+ }
+ } else {
+ struct gl_shader_storage_buffer_binding *binding;
+ binding =
+ &ctx->ShaderStorageBufferBindings[shader->UniformBlocks[i].Binding];
+ if (binding->BufferObject == ctx->Shared->NullBufferObj) {
+ brw->vtbl.emit_null_surface_state(brw, 1, 1, 1, &surf_offsets[i]);
+ } else {
+ intel_bo = intel_buffer_object(binding->BufferObject);
+ drm_intel_bo *bo =
+ intel_bufferobj_buffer(brw, intel_bo,
+ binding->Offset,
+ binding->BufferObject->Size - binding->Offset);
+ brw_create_buffer_surface(brw, bo, binding->Offset,
+ binding->BufferObject->Size - binding->Offset,
+ &surf_offsets[i],
+ dword_pitch);
+ }
+ }
}
if (shader->NumUniformBlocks)
.emit = brw_upload_wm_ubo_surfaces,
};
+static void
+brw_upload_cs_ubo_surfaces(struct brw_context *brw)
+{
+ struct gl_context *ctx = &brw->ctx;
+ /* _NEW_PROGRAM */
+ struct gl_shader_program *prog =
+ ctx->_Shader->CurrentProgram[MESA_SHADER_COMPUTE];
+
+ if (!prog)
+ return;
+
+ /* BRW_NEW_CS_PROG_DATA */
+ brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_COMPUTE],
+ &brw->cs.base, &brw->cs.prog_data->base, true);
+}
+
+const struct brw_tracked_state brw_cs_ubo_surfaces = {
+ .dirty = {
+ .mesa = _NEW_PROGRAM,
+ .brw = BRW_NEW_BATCH |
+ BRW_NEW_CS_PROG_DATA |
+ BRW_NEW_UNIFORM_BUFFER,
+ },
+ .emit = brw_upload_cs_ubo_surfaces,
+};
+
void
brw_upload_abo_surfaces(struct brw_context *brw,
struct gl_shader_program *prog,
uint32_t *surf_offsets =
&stage_state->surf_offset[prog_data->binding_table.abo_start];
- for (int i = 0; i < prog->NumAtomicBuffers; i++) {
+ for (unsigned i = 0; i < prog->NumAtomicBuffers; i++) {
struct gl_atomic_buffer_binding *binding =
&ctx->AtomicBufferBindings[prog->AtomicBuffers[i].Binding];
struct intel_buffer_object *intel_bo =
.emit = brw_upload_cs_abo_surfaces,
};
+static void
+brw_upload_cs_image_surfaces(struct brw_context *brw)
+{
+ struct gl_context *ctx = &brw->ctx;
+ /* _NEW_PROGRAM */
+ struct gl_shader_program *prog =
+ ctx->_Shader->CurrentProgram[MESA_SHADER_COMPUTE];
+
+ if (prog) {
+ /* BRW_NEW_CS_PROG_DATA, BRW_NEW_IMAGE_UNITS */
+ brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_COMPUTE],
+ &brw->cs.base, &brw->cs.prog_data->base);
+ }
+}
+
+const struct brw_tracked_state brw_cs_image_surfaces = {
+ .dirty = {
+ .mesa = _NEW_PROGRAM,
+ .brw = BRW_NEW_BATCH |
+ BRW_NEW_CS_PROG_DATA |
+ BRW_NEW_IMAGE_UNITS
+ },
+ .emit = brw_upload_cs_image_surfaces,
+};
+
static uint32_t
get_image_format(struct brw_context *brw, mesa_format format, GLenum access)
{
minify(mt->logical_depth0, u->Level) :
mt->logical_depth0);
- intel_miptree_get_image_offset(mt, u->Level, u->Layer,
+ intel_miptree_get_image_offset(mt, u->Level, u->_Layer,
¶m->offset[0],
¶m->offset[1]);
access != GL_READ_ONLY);
} else {
- const unsigned min_layer = obj->MinLayer + u->Layer;
+ const unsigned min_layer = obj->MinLayer + u->_Layer;
const unsigned min_level = obj->MinLevel + u->Level;
const unsigned num_layers = (!u->Layered ? 1 :
obj->Target == GL_TEXTURE_CUBE_MAP ? 6 :
}
}
+void
+brw_upload_image_surfaces(struct brw_context *brw,
+ struct gl_shader *shader,
+ struct brw_stage_state *stage_state,
+ struct brw_stage_prog_data *prog_data)
+{
+ struct gl_context *ctx = &brw->ctx;
+
+ if (shader && shader->NumImages) {
+ for (unsigned i = 0; i < shader->NumImages; i++) {
+ struct gl_image_unit *u = &ctx->ImageUnits[shader->ImageUnits[i]];
+ const unsigned surf_idx = prog_data->binding_table.image_start + i;
+
+ update_image_surface(brw, u, shader->ImageAccess[i],
+ surf_idx,
+ &stage_state->surf_offset[surf_idx],
+ &prog_data->image_param[i]);
+ }
+
+ brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
+ }
+}
+
+static void
+brw_upload_wm_image_surfaces(struct brw_context *brw)
+{
+ struct gl_context *ctx = &brw->ctx;
+ /* BRW_NEW_FRAGMENT_PROGRAM */
+ struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram;
+
+ if (prog) {
+ /* BRW_NEW_FS_PROG_DATA, BRW_NEW_IMAGE_UNITS */
+ brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
+ &brw->wm.base, &brw->wm.prog_data->base);
+ }
+}
+
+const struct brw_tracked_state brw_wm_image_surfaces = {
+ .dirty = {
+ .brw = BRW_NEW_BATCH |
+ BRW_NEW_FRAGMENT_PROGRAM |
+ BRW_NEW_FS_PROG_DATA |
+ BRW_NEW_IMAGE_UNITS
+ },
+ .emit = brw_upload_wm_image_surfaces,
+};
+
void
gen4_init_vtable_surface_functions(struct brw_context *brw)
{
brw->vtbl.emit_null_surface_state = brw_emit_null_surface_state;
brw->vtbl.emit_buffer_surface_state = gen4_emit_buffer_surface_state;
}
+
+static void
+brw_upload_cs_work_groups_surface(struct brw_context *brw)
+{
+ struct gl_context *ctx = &brw->ctx;
+ /* _NEW_PROGRAM */
+ struct gl_shader_program *prog =
+ ctx->_Shader->CurrentProgram[MESA_SHADER_COMPUTE];
+
+ if (prog && brw->cs.prog_data->uses_num_work_groups) {
+ const unsigned surf_idx =
+ brw->cs.prog_data->binding_table.work_groups_start;
+ uint32_t *surf_offset = &brw->cs.base.surf_offset[surf_idx];
+ drm_intel_bo *bo;
+ uint32_t bo_offset;
+
+ if (brw->compute.num_work_groups_bo == NULL) {
+ bo = NULL;
+ intel_upload_data(brw,
+ (void *)brw->compute.num_work_groups,
+ 3 * sizeof(GLuint),
+ sizeof(GLuint),
+ &bo,
+ &bo_offset);
+ } else {
+ bo = brw->compute.num_work_groups_bo;
+ bo_offset = brw->compute.num_work_groups_offset;
+ }
+
+ brw->vtbl.emit_buffer_surface_state(brw, surf_offset,
+ bo, bo_offset,
+ BRW_SURFACEFORMAT_RAW,
+ 3 * sizeof(GLuint), 1, true);
+ brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
+ }
+}
+
+const struct brw_tracked_state brw_cs_work_groups_surface = {
+ .dirty = {
+ .brw = BRW_NEW_CS_WORK_GROUPS
+ },
+ .emit = brw_upload_cs_work_groups_surface,
+};
projects / mesa.git / blobdiff