/*
Copyright (C) Intel Corp. 2006. All Rights Reserved.
- Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
+ Intel funded Tungsten Graphics to
develop this 3D driver.
-
+
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
-
+
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
-
+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
+
**********************************************************************/
/*
* Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
+ * Keith Whitwell <keithw@vmware.com>
*/
-
+
#include "main/context.h"
#include "main/blend.h"
translate_tex_target(GLenum target)
{
switch (target) {
- case GL_TEXTURE_1D:
+ case GL_TEXTURE_1D:
case GL_TEXTURE_1D_ARRAY_EXT:
return BRW_SURFACE_1D;
- case GL_TEXTURE_RECTANGLE_NV:
+ case GL_TEXTURE_RECTANGLE_NV:
return BRW_SURFACE_2D;
- case GL_TEXTURE_2D:
+ case GL_TEXTURE_2D:
case GL_TEXTURE_2D_ARRAY_EXT:
case GL_TEXTURE_EXTERNAL_OES:
case GL_TEXTURE_2D_MULTISAMPLE:
case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
return BRW_SURFACE_2D;
- case GL_TEXTURE_3D:
+ case GL_TEXTURE_3D:
return BRW_SURFACE_3D;
- case GL_TEXTURE_CUBE_MAP:
+ case GL_TEXTURE_CUBE_MAP:
case GL_TEXTURE_CUBE_MAP_ARRAY:
return BRW_SURFACE_CUBE;
- default:
- assert(0);
+ default:
+ assert(0);
return 0;
}
}
return BRW_SURFACE_MULTISAMPLECOUNT_1;
}
+void
+brw_configure_w_tiled(const struct intel_mipmap_tree *mt,
+ bool is_render_target,
+ unsigned *width, unsigned *height,
+ unsigned *pitch, uint32_t *tiling, unsigned *format)
+{
+ static const unsigned halign_stencil = 8;
+
+ /* In Y-tiling row is twice as wide as in W-tiling, and subsequently
+ * there are half as many rows.
+ * In addition, mip-levels are accessed manually by the program and
+ * therefore the surface is setup to cover all the mip-levels for one slice.
+ * (Hardware is still used to access individual slices).
+ */
+ *tiling = I915_TILING_Y;
+ *pitch = mt->pitch * 2;
+ *width = ALIGN(mt->total_width, halign_stencil) * 2;
+ *height = (mt->total_height / mt->physical_depth0) / 2;
+
+ if (is_render_target) {
+ *format = BRW_SURFACEFORMAT_R8_UINT;
+ }
+}
+
/**
* Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
swizzles[GET_SWZ(t->_Swizzle, 3)]);
}
-
static void
+gen4_emit_buffer_surface_state(struct brw_context *brw,
+ uint32_t *out_offset,
+ drm_intel_bo *bo,
+ unsigned buffer_offset,
+ unsigned surface_format,
+ unsigned buffer_size,
+ unsigned pitch,
+ unsigned mocs,
+ bool rw)
+{
+ uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ 6 * 4, 32, out_offset);
+ memset(surf, 0, 6 * 4);
+
+ surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
+ surface_format << BRW_SURFACE_FORMAT_SHIFT |
+ (brw->gen >= 6 ? BRW_SURFACE_RC_READ_WRITE : 0);
+ surf[1] = (bo ? bo->offset64 : 0) + buffer_offset; /* reloc */
+ surf[2] = (buffer_size & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
+ ((buffer_size >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT;
+ surf[3] = ((buffer_size >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
+ (pitch - 1) << BRW_SURFACE_PITCH_SHIFT;
+
+ /* Emit relocation to surface contents. The 965 PRM, Volume 4, section
+ * 5.1.2 "Data Cache" says: "the data cache does not exist as a separate
+ * physical cache. It is mapped in hardware to the sampler cache."
+ */
+ if (bo) {
+ drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 4,
+ bo, buffer_offset,
+ I915_GEM_DOMAIN_SAMPLER,
+ (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
+ }
+}
+
+void
brw_update_buffer_texture_surface(struct gl_context *ctx,
unsigned unit,
- uint32_t *binding_table,
- unsigned surf_index)
+ uint32_t *surf_offset)
{
struct brw_context *brw = brw_context(ctx);
- struct intel_context *intel = &brw->intel;
struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
- uint32_t *surf;
struct intel_buffer_object *intel_obj =
intel_buffer_object(tObj->BufferObject);
- drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
- gl_format format = tObj->_BufferObjectFormat;
+ uint32_t size = tObj->BufferSize;
+ drm_intel_bo *bo = NULL;
+ mesa_format format = tObj->_BufferObjectFormat;
uint32_t brw_format = brw_format_for_mesa_format(format);
int texel_size = _mesa_get_format_bytes(format);
+ if (intel_obj) {
+ size = MIN2(size, intel_obj->Base.Size);
+ bo = intel_bufferobj_buffer(brw, intel_obj, tObj->BufferOffset, size);
+ }
+
if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
_mesa_problem(NULL, "bad format %s for texture buffer\n",
_mesa_get_format_name(format));
}
- surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 6 * 4, 32, &binding_table[surf_index]);
-
- surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
- (brw_format_for_mesa_format(format) << BRW_SURFACE_FORMAT_SHIFT));
-
- if (intel->gen >= 6)
- surf[0] |= BRW_SURFACE_RC_READ_WRITE;
-
- if (bo) {
- surf[1] = bo->offset; /* reloc */
-
- /* Emit relocation to surface contents. */
- drm_intel_bo_emit_reloc(brw->intel.batch.bo,
- binding_table[surf_index] + 4,
- bo, 0, I915_GEM_DOMAIN_SAMPLER, 0);
-
- int w = intel_obj->Base.Size / texel_size;
- surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
- ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
- surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
- (texel_size - 1) << BRW_SURFACE_PITCH_SHIFT);
- } else {
- surf[1] = 0;
- surf[2] = 0;
- surf[3] = 0;
- }
-
- surf[4] = 0;
- surf[5] = 0;
+ brw->vtbl.emit_buffer_surface_state(brw, surf_offset, bo,
+ tObj->BufferOffset,
+ brw_format,
+ size / texel_size,
+ texel_size,
+ 0, /* mocs */
+ false /* rw */);
}
static void
brw_update_texture_surface(struct gl_context *ctx,
unsigned unit,
- uint32_t *binding_table,
- unsigned surf_index)
+ uint32_t *surf_offset,
+ bool for_gather)
{
struct brw_context *brw = brw_context(ctx);
struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
struct intel_texture_object *intelObj = intel_texture_object(tObj);
struct intel_mipmap_tree *mt = intelObj->mt;
- struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
uint32_t *surf;
- uint32_t tile_x, tile_y;
+ /* BRW_NEW_UNIFORM_BUFFER */
if (tObj->Target == GL_TEXTURE_BUFFER) {
- brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
+ brw_update_buffer_texture_surface(ctx, unit, surf_offset);
return;
}
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 6 * 4, 32, &binding_table[surf_index]);
+ 6 * 4, 32, surf_offset);
+
+ uint32_t tex_format = translate_tex_format(brw, mt->format,
+ sampler->sRGBDecode);
+
+ if (for_gather) {
+ /* Sandybridge's gather4 message is broken for integer formats.
+ * To work around this, we pretend the surface is UNORM for
+ * 8 or 16-bit formats, and emit shader instructions to recover
+ * the real INT/UINT value. For 32-bit formats, we pretend
+ * the surface is FLOAT, and simply reinterpret the resulting
+ * bits.
+ */
+ switch (tex_format) {
+ case BRW_SURFACEFORMAT_R8_SINT:
+ case BRW_SURFACEFORMAT_R8_UINT:
+ tex_format = BRW_SURFACEFORMAT_R8_UNORM;
+ break;
+
+ case BRW_SURFACEFORMAT_R16_SINT:
+ case BRW_SURFACEFORMAT_R16_UINT:
+ tex_format = BRW_SURFACEFORMAT_R16_UNORM;
+ break;
+
+ case BRW_SURFACEFORMAT_R32_SINT:
+ case BRW_SURFACEFORMAT_R32_UINT:
+ tex_format = BRW_SURFACEFORMAT_R32_FLOAT;
+ break;
+
+ default:
+ break;
+ }
+ }
surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
BRW_SURFACE_CUBEFACE_ENABLES |
- (translate_tex_format(brw,
- mt->format,
- tObj->DepthMode,
- sampler->sRGBDecode) <<
- BRW_SURFACE_FORMAT_SHIFT));
+ tex_format << BRW_SURFACE_FORMAT_SHIFT);
- surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */
- surf[1] += intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
- &tile_x, &tile_y);
+ surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
(mt->logical_width0 - 1) << BRW_SURFACE_WIDTH_SHIFT |
(mt->logical_height0 - 1) << BRW_SURFACE_HEIGHT_SHIFT);
- surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
+ surf[3] = (brw_get_surface_tiling_bits(mt->tiling) |
(mt->logical_depth0 - 1) << BRW_SURFACE_DEPTH_SHIFT |
- (intelObj->mt->region->pitch - 1) <<
- BRW_SURFACE_PITCH_SHIFT);
+ (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
- surf[4] = brw_get_surface_num_multisamples(intelObj->mt->num_samples);
+ surf[4] = (brw_get_surface_num_multisamples(mt->num_samples) |
+ SET_FIELD(tObj->BaseLevel - mt->first_level, BRW_SURFACE_MIN_LOD));
- assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
- /* Note that the low bits of these fields are missing, so
- * there's the possibility of getting in trouble.
- */
- assert(tile_x % 4 == 0);
- assert(tile_y % 2 == 0);
- surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
- (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
- (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
+ surf[5] = mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
/* Emit relocation to surface contents */
- drm_intel_bo_emit_reloc(brw->intel.batch.bo,
- binding_table[surf_index] + 4,
- intelObj->mt->region->bo,
- surf[1] - intelObj->mt->region->bo->offset,
- I915_GEM_DOMAIN_SAMPLER, 0);
+ drm_intel_bo_emit_reloc(brw->batch.bo,
+ *surf_offset + 4,
+ mt->bo,
+ surf[1] - mt->bo->offset64,
+ I915_GEM_DOMAIN_SAMPLER, 0);
}
/**
* Create the constant buffer surface. Vertex/fragment shader constants will be
* read from this buffer with Data Port Read instructions/messages.
*/
-static void
+void
brw_create_constant_surface(struct brw_context *brw,
drm_intel_bo *bo,
uint32_t offset,
uint32_t *out_offset,
bool dword_pitch)
{
- struct intel_context *intel = &brw->intel;
uint32_t stride = dword_pitch ? 4 : 16;
uint32_t elements = ALIGN(size, stride) / stride;
- const GLint w = elements - 1;
- uint32_t *surf;
-
- surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 6 * 4, 32, out_offset);
-
- surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
- BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
- BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
-
- if (intel->gen >= 6)
- surf[0] |= BRW_SURFACE_RC_READ_WRITE;
- surf[1] = bo->offset + offset; /* reloc */
-
- surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
- ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
-
- surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
- (stride - 1) << BRW_SURFACE_PITCH_SHIFT);
-
- surf[4] = 0;
- surf[5] = 0;
-
- /* Emit relocation to surface contents. Section 5.1.1 of the gen4
- * bspec ("Data Cache") says that the data cache does not exist as
- * a separate cache and is just the sampler cache.
- */
- drm_intel_bo_emit_reloc(brw->intel.batch.bo,
- *out_offset + 4,
- bo, offset,
- I915_GEM_DOMAIN_SAMPLER, 0);
+ brw->vtbl.emit_buffer_surface_state(brw, out_offset, bo, offset,
+ BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
+ elements, stride, 0, false);
}
/**
uint32_t *out_offset, unsigned num_vector_components,
unsigned stride_dwords, unsigned offset_dwords)
{
- struct intel_context *intel = &brw->intel;
struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj);
- drm_intel_bo *bo = intel_bufferobj_buffer(brw, intel_bo, INTEL_WRITE_PART);
+ uint32_t offset_bytes = 4 * offset_dwords;
+ drm_intel_bo *bo = intel_bufferobj_buffer(brw, intel_bo,
+ offset_bytes,
+ buffer_obj->Size - offset_bytes);
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
out_offset);
uint32_t pitch_minus_1 = 4*stride_dwords - 1;
- uint32_t offset_bytes = 4 * offset_dwords;
size_t size_dwords = buffer_obj->Size / 4;
uint32_t buffer_size_minus_1, width, height, depth, surface_format;
BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
surface_format << BRW_SURFACE_FORMAT_SHIFT |
BRW_SURFACE_RC_READ_WRITE;
- surf[1] = bo->offset + offset_bytes; /* reloc */
+ surf[1] = bo->offset64 + offset_bytes; /* reloc */
surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
height << BRW_SURFACE_HEIGHT_SHIFT);
surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
surf[5] = 0;
/* Emit relocation to surface contents. */
- drm_intel_bo_emit_reloc(brw->intel.batch.bo,
+ drm_intel_bo_emit_reloc(brw->batch.bo,
*out_offset + 4,
bo, offset_bytes,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
static void
brw_upload_wm_pull_constants(struct brw_context *brw)
{
- struct gl_context *ctx = &brw->intel.ctx;
- struct intel_context *intel = &brw->intel;
+ struct gl_context *ctx = &brw->ctx;
/* BRW_NEW_FRAGMENT_PROGRAM */
struct brw_fragment_program *fp =
(struct brw_fragment_program *) brw->fragment_program;
struct gl_program_parameter_list *params = fp->program.Base.Parameters;
- const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
- const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
- float *constants;
+ const int size = brw->wm.prog_data->base.nr_pull_params * sizeof(float);
+ const int surf_index =
+ brw->wm.prog_data->base.binding_table.pull_constants_start;
unsigned int i;
_mesa_load_state_parameters(ctx, params);
/* CACHE_NEW_WM_PROG */
- if (brw->wm.prog_data->nr_pull_params == 0) {
- if (brw->wm.const_bo) {
- drm_intel_bo_unreference(brw->wm.const_bo);
- brw->wm.const_bo = NULL;
- brw->wm.surf_offset[surf_index] = 0;
+ if (brw->wm.prog_data->base.nr_pull_params == 0) {
+ if (brw->wm.base.surf_offset[surf_index]) {
+ brw->wm.base.surf_offset[surf_index] = 0;
brw->state.dirty.brw |= BRW_NEW_SURFACES;
}
return;
}
- drm_intel_bo_unreference(brw->wm.const_bo);
- brw->wm.const_bo = drm_intel_bo_alloc(brw->bufmgr, "WM const bo",
- size, 64);
-
/* _NEW_PROGRAM_CONSTANTS */
- drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
- constants = brw->wm.const_bo->virtual;
- for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
- constants[i] = *brw->wm.prog_data->pull_param[i];
+ drm_intel_bo *const_bo = NULL;
+ uint32_t const_offset;
+ float *constants = intel_upload_space(brw, size, 64,
+ &const_bo, &const_offset);
+ for (i = 0; i < brw->wm.prog_data->base.nr_pull_params; i++) {
+ constants[i] = *brw->wm.prog_data->base.pull_param[i];
}
- drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
- brw->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0, size,
- &brw->wm.surf_offset[surf_index],
- true);
+ brw_create_constant_surface(brw, const_bo, const_offset, size,
+ &brw->wm.base.surf_offset[surf_index],
+ true);
+ drm_intel_bo_unreference(const_bo);
brw->state.dirty.brw |= BRW_NEW_SURFACES;
}
*
* - Surface Format must be R8G8B8A8_UNORM.
*/
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &intel->ctx;
+ struct gl_context *ctx = &brw->ctx;
uint32_t *surf;
unsigned surface_type = BRW_SURFACE_NULL;
drm_intel_bo *bo = NULL;
unsigned pitch_minus_1 = 0;
uint32_t multisampling_state = 0;
+ uint32_t surf_index =
+ brw->wm.prog_data->binding_table.render_target_start + unit;
/* _NEW_BUFFERS */
const struct gl_framebuffer *fb = ctx->DrawBuffer;
- surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 6 * 4, 32, &brw->wm.surf_offset[unit]);
+ surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
+ &brw->wm.base.surf_offset[surf_index]);
if (fb->Visual.samples > 1) {
/* On Gen6, null render targets seem to cause GPU hangs when
surf[0] = (surface_type << BRW_SURFACE_TYPE_SHIFT |
BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
- if (intel->gen < 6) {
+ if (brw->gen < 6) {
surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
}
- surf[1] = bo ? bo->offset : 0;
+ surf[1] = bo ? bo->offset64 : 0;
surf[2] = ((fb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(fb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
surf[5] = 0;
if (bo) {
- drm_intel_bo_emit_reloc(brw->intel.batch.bo,
- brw->wm.surf_offset[unit] + 4,
+ drm_intel_bo_emit_reloc(brw->batch.bo,
+ brw->wm.base.surf_offset[surf_index] + 4,
bo, 0,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
}
bool layered,
unsigned int unit)
{
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &intel->ctx;
+ struct gl_context *ctx = &brw->ctx;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_mipmap_tree *mt = irb->mt;
- struct intel_region *region;
uint32_t *surf;
uint32_t tile_x, tile_y;
uint32_t format = 0;
/* _NEW_BUFFERS */
- gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
+ mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
+ uint32_t surf_index =
+ brw->wm.prog_data->binding_table.render_target_start + unit;
assert(!layered);
intel_miptree_used_for_rendering(irb->mt);
- region = irb->mt->region;
-
- surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 6 * 4, 32, &brw->wm.surf_offset[unit]);
+ surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
+ &brw->wm.base.surf_offset[surf_index]);
format = brw->render_target_format[rb_format];
if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
/* reloc */
surf[1] = (intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) +
- region->bo->offset);
+ mt->bo->offset64);
surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
- surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
- (region->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
+ surf[3] = (brw_get_surface_tiling_bits(mt->tiling) |
+ (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
(tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
(mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
- if (intel->gen < 6) {
+ if (brw->gen < 6) {
/* _NEW_COLOR */
if (!ctx->Color.ColorLogicOpEnabled &&
(ctx->Color.BlendEnabled & (1 << unit)))
}
}
- drm_intel_bo_emit_reloc(brw->intel.batch.bo,
- brw->wm.surf_offset[unit] + 4,
- region->bo,
- surf[1] - region->bo->offset,
+ drm_intel_bo_emit_reloc(brw->batch.bo,
+ brw->wm.base.surf_offset[surf_index] + 4,
+ mt->bo,
+ surf[1] - mt->bo->offset64,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER);
}
static void
brw_update_renderbuffer_surfaces(struct brw_context *brw)
{
- struct gl_context *ctx = &brw->intel.ctx;
+ struct gl_context *ctx = &brw->ctx;
GLuint i;
/* _NEW_BUFFERS | _NEW_COLOR */
for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
brw->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i],
- ctx->DrawBuffer->Layered, i);
+ ctx->DrawBuffer->MaxNumLayers > 0, i);
} else {
brw->vtbl.update_null_renderbuffer_surface(brw, i);
}
.emit = brw_update_renderbuffer_surfaces,
};
-/**
- * Construct SURFACE_STATE objects for enabled textures.
- */
+
static void
-brw_update_texture_surfaces(struct brw_context *brw)
+update_stage_texture_surfaces(struct brw_context *brw,
+ const struct gl_program *prog,
+ struct brw_stage_state *stage_state,
+ bool for_gather)
{
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &intel->ctx;
-
- /* BRW_NEW_VERTEX_PROGRAM and BRW_NEW_FRAGMENT_PROGRAM:
- * Unfortunately, we're stuck using the gl_program structs until the
- * ARB_fragment_program front-end gets converted to GLSL IR. These
- * have the downside that SamplerUnits is split and only contains the
- * mappings for samplers active in that stage.
- */
- struct gl_program *vs = (struct gl_program *) brw->vertex_program;
- struct gl_program *fs = (struct gl_program *) brw->fragment_program;
+ if (!prog)
+ return;
+
+ struct gl_context *ctx = &brw->ctx;
- unsigned num_samplers = _mesa_fls(vs->SamplersUsed | fs->SamplersUsed);
+ uint32_t *surf_offset = stage_state->surf_offset;
+ if (for_gather)
+ surf_offset += stage_state->prog_data->binding_table.gather_texture_start;
+ else
+ surf_offset += stage_state->prog_data->binding_table.texture_start;
+ unsigned num_samplers = _mesa_fls(prog->SamplersUsed);
for (unsigned s = 0; s < num_samplers; s++) {
- brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(s)] = 0;
- brw->wm.surf_offset[SURF_INDEX_TEXTURE(s)] = 0;
+ surf_offset[s] = 0;
- if (vs->SamplersUsed & (1 << s)) {
- const unsigned unit = vs->SamplerUnits[s];
+ if (prog->SamplersUsed & (1 << s)) {
+ const unsigned unit = prog->SamplerUnits[s];
/* _NEW_TEXTURE */
- if (ctx->Texture.Unit[unit]._ReallyEnabled) {
- brw->vtbl.update_texture_surface(ctx, unit,
- brw->vs.surf_offset,
- SURF_INDEX_VS_TEXTURE(s));
+ if (ctx->Texture.Unit[unit]._Current) {
+ brw->vtbl.update_texture_surface(ctx, unit, surf_offset + s, for_gather);
}
}
+ }
+}
- if (fs->SamplersUsed & (1 << s)) {
- const unsigned unit = fs->SamplerUnits[s];
- /* _NEW_TEXTURE */
- if (ctx->Texture.Unit[unit]._ReallyEnabled) {
- brw->vtbl.update_texture_surface(ctx, unit,
- brw->wm.surf_offset,
- SURF_INDEX_TEXTURE(s));
- }
- }
- }
+/**
+ * Construct SURFACE_STATE objects for enabled textures.
+ */
+static void
+brw_update_texture_surfaces(struct brw_context *brw)
+{
+ /* BRW_NEW_VERTEX_PROGRAM */
+ struct gl_program *vs = (struct gl_program *) brw->vertex_program;
+
+ /* BRW_NEW_GEOMETRY_PROGRAM */
+ struct gl_program *gs = (struct gl_program *) brw->geometry_program;
+
+ /* BRW_NEW_FRAGMENT_PROGRAM */
+ struct gl_program *fs = (struct gl_program *) brw->fragment_program;
+
+ /* _NEW_TEXTURE */
+ update_stage_texture_surfaces(brw, vs, &brw->vs.base, false);
+ update_stage_texture_surfaces(brw, gs, &brw->gs.base, false);
+ update_stage_texture_surfaces(brw, fs, &brw->wm.base, false);
+
+ /* emit alternate set of surface state for gather. this
+ * allows the surface format to be overriden for only the
+ * gather4 messages. */
+ if (vs && vs->UsesGather)
+ update_stage_texture_surfaces(brw, vs, &brw->vs.base, true);
+ if (gs && gs->UsesGather)
+ update_stage_texture_surfaces(brw, gs, &brw->gs.base, true);
+ if (fs && fs->UsesGather)
+ update_stage_texture_surfaces(brw, fs, &brw->wm.base, true);
brw->state.dirty.brw |= BRW_NEW_SURFACES;
}
.dirty = {
.mesa = _NEW_TEXTURE,
.brw = BRW_NEW_BATCH |
+ BRW_NEW_UNIFORM_BUFFER |
BRW_NEW_VERTEX_PROGRAM |
+ BRW_NEW_GEOMETRY_PROGRAM |
BRW_NEW_FRAGMENT_PROGRAM,
.cache = 0
},
void
brw_upload_ubo_surfaces(struct brw_context *brw,
struct gl_shader *shader,
- uint32_t *surf_offsets)
+ struct brw_stage_state *stage_state,
+ struct brw_stage_prog_data *prog_data)
{
- struct gl_context *ctx = &brw->intel.ctx;
+ struct gl_context *ctx = &brw->ctx;
if (!shader)
return;
+ uint32_t *surf_offsets =
+ &stage_state->surf_offset[prog_data->binding_table.ubo_start];
+
for (int i = 0; i < shader->NumUniformBlocks; i++) {
struct gl_uniform_buffer_binding *binding;
struct intel_buffer_object *intel_bo;
binding = &ctx->UniformBufferBindings[shader->UniformBlocks[i].Binding];
intel_bo = intel_buffer_object(binding->BufferObject);
- drm_intel_bo *bo = intel_bufferobj_buffer(brw, intel_bo, INTEL_READ);
+ drm_intel_bo *bo =
+ intel_bufferobj_buffer(brw, intel_bo,
+ binding->Offset,
+ binding->BufferObject->Size - binding->Offset);
/* Because behavior for referencing outside of the binding's size in the
* glBindBufferRange case is undefined, we can just bind the whole buffer
* glBindBufferBase wants and be a correct implementation.
*/
- brw->vtbl.create_constant_surface(brw, bo, binding->Offset,
- bo->size - binding->Offset,
- &surf_offsets[i],
- shader->Type == GL_FRAGMENT_SHADER);
+ brw_create_constant_surface(brw, bo, binding->Offset,
+ bo->size - binding->Offset,
+ &surf_offsets[i],
+ shader->Stage == MESA_SHADER_FRAGMENT);
}
if (shader->NumUniformBlocks)
static void
brw_upload_wm_ubo_surfaces(struct brw_context *brw)
{
- struct gl_context *ctx = &brw->intel.ctx;
+ struct gl_context *ctx = &brw->ctx;
/* _NEW_PROGRAM */
- struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram;
+ struct gl_shader_program *prog = ctx->_Shader->_CurrentFragmentProgram;
if (!prog)
return;
+ /* CACHE_NEW_WM_PROG */
brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
- &brw->wm.surf_offset[SURF_INDEX_WM_UBO(0)]);
+ &brw->wm.base, &brw->wm.prog_data->base);
}
const struct brw_tracked_state brw_wm_ubo_surfaces = {
.dirty = {
.mesa = _NEW_PROGRAM,
.brw = BRW_NEW_BATCH | BRW_NEW_UNIFORM_BUFFER,
- .cache = 0,
+ .cache = CACHE_NEW_WM_PROG,
},
.emit = brw_upload_wm_ubo_surfaces,
};
-/**
- * Constructs the binding table for the WM surface state, which maps unit
- * numbers to surface state objects.
- */
-static void
-brw_upload_wm_binding_table(struct brw_context *brw)
+void
+brw_upload_abo_surfaces(struct brw_context *brw,
+ struct gl_shader_program *prog,
+ struct brw_stage_state *stage_state,
+ struct brw_stage_prog_data *prog_data)
{
- uint32_t *bind;
- int i;
-
- if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
- gen7_create_shader_time_surface(brw, &brw->wm.surf_offset[SURF_INDEX_WM_SHADER_TIME]);
+ struct gl_context *ctx = &brw->ctx;
+ uint32_t *surf_offsets =
+ &stage_state->surf_offset[prog_data->binding_table.abo_start];
+
+ for (int i = 0; i < prog->NumAtomicBuffers; i++) {
+ struct gl_atomic_buffer_binding *binding =
+ &ctx->AtomicBufferBindings[prog->AtomicBuffers[i].Binding];
+ struct intel_buffer_object *intel_bo =
+ intel_buffer_object(binding->BufferObject);
+ drm_intel_bo *bo = intel_bufferobj_buffer(
+ brw, intel_bo, binding->Offset, intel_bo->Base.Size - binding->Offset);
+
+ brw->vtbl.create_raw_surface(brw, bo, binding->Offset,
+ bo->size - binding->Offset,
+ &surf_offsets[i], true);
}
- /* Might want to calculate nr_surfaces first, to avoid taking up so much
- * space for the binding table.
- */
- bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
- sizeof(uint32_t) * BRW_MAX_WM_SURFACES,
- 32, &brw->wm.bind_bo_offset);
+ if (prog->NumUniformBlocks)
+ brw->state.dirty.brw |= BRW_NEW_SURFACES;
+}
- /* BRW_NEW_SURFACES */
- for (i = 0; i < BRW_MAX_WM_SURFACES; i++) {
- bind[i] = brw->wm.surf_offset[i];
- }
+static void
+brw_upload_wm_abo_surfaces(struct brw_context *brw)
+{
+ struct gl_context *ctx = &brw->ctx;
+ /* _NEW_PROGRAM */
+ struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram;
- brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
+ if (prog) {
+ /* CACHE_NEW_WM_PROG */
+ brw_upload_abo_surfaces(brw, prog, &brw->wm.base,
+ &brw->wm.prog_data->base);
+ }
}
-const struct brw_tracked_state brw_wm_binding_table = {
+const struct brw_tracked_state brw_wm_abo_surfaces = {
.dirty = {
- .mesa = 0,
- .brw = (BRW_NEW_BATCH |
- BRW_NEW_SURFACES),
- .cache = 0
+ .mesa = _NEW_PROGRAM,
+ .brw = BRW_NEW_BATCH | BRW_NEW_ATOMIC_BUFFER,
+ .cache = CACHE_NEW_WM_PROG,
},
- .emit = brw_upload_wm_binding_table,
+ .emit = brw_upload_wm_abo_surfaces,
};
void
brw->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
brw->vtbl.update_null_renderbuffer_surface =
brw_update_null_renderbuffer_surface;
- brw->vtbl.create_constant_surface = brw_create_constant_surface;
+ brw->vtbl.emit_buffer_surface_state = gen4_emit_buffer_surface_state;
}
projects / mesa.git / blobdiff