/*
Copyright (C) Intel Corp. 2006. All Rights Reserved.
- Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
+ Intel funded Tungsten Graphics to
develop this 3D driver.
-
+
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
-
+
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
-
+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
+
**********************************************************************/
/*
* Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
+ * Keith Whitwell <keithw@vmware.com>
*/
-
+
#include "main/context.h"
#include "main/blend.h"
translate_tex_target(GLenum target)
{
switch (target) {
- case GL_TEXTURE_1D:
+ case GL_TEXTURE_1D:
case GL_TEXTURE_1D_ARRAY_EXT:
return BRW_SURFACE_1D;
- case GL_TEXTURE_RECTANGLE_NV:
+ case GL_TEXTURE_RECTANGLE_NV:
return BRW_SURFACE_2D;
- case GL_TEXTURE_2D:
+ case GL_TEXTURE_2D:
case GL_TEXTURE_2D_ARRAY_EXT:
case GL_TEXTURE_EXTERNAL_OES:
case GL_TEXTURE_2D_MULTISAMPLE:
case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
return BRW_SURFACE_2D;
- case GL_TEXTURE_3D:
+ case GL_TEXTURE_3D:
return BRW_SURFACE_3D;
- case GL_TEXTURE_CUBE_MAP:
+ case GL_TEXTURE_CUBE_MAP:
case GL_TEXTURE_CUBE_MAP_ARRAY:
return BRW_SURFACE_CUBE;
- default:
- assert(0);
+ default:
+ assert(0);
return 0;
}
}
return BRW_SURFACE_MULTISAMPLECOUNT_1;
}
+void
+brw_configure_w_tiled(const struct intel_mipmap_tree *mt,
+ bool is_render_target,
+ unsigned *width, unsigned *height,
+ unsigned *pitch, uint32_t *tiling, unsigned *format)
+{
+ static const unsigned halign_stencil = 8;
+
+ /* In Y-tiling row is twice as wide as in W-tiling, and subsequently
+ * there are half as many rows.
+ * In addition, mip-levels are accessed manually by the program and
+ * therefore the surface is setup to cover all the mip-levels for one slice.
+ * (Hardware is still used to access individual slices).
+ */
+ *tiling = I915_TILING_Y;
+ *pitch = mt->pitch * 2;
+ *width = ALIGN(mt->total_width, halign_stencil) * 2;
+ *height = (mt->total_height / mt->physical_depth0) / 2;
+
+ if (is_render_target) {
+ *format = BRW_SURFACEFORMAT_R8_UINT;
+ }
+}
+
/**
* Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
surface_format << BRW_SURFACE_FORMAT_SHIFT |
(brw->gen >= 6 ? BRW_SURFACE_RC_READ_WRITE : 0);
- surf[1] = (bo ? bo->offset : 0) + buffer_offset; /* reloc */
+ surf[1] = (bo ? bo->offset64 : 0) + buffer_offset; /* reloc */
surf[2] = (buffer_size & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
((buffer_size >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT;
surf[3] = ((buffer_size >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
intel_buffer_object(tObj->BufferObject);
uint32_t size = tObj->BufferSize;
drm_intel_bo *bo = NULL;
- gl_format format = tObj->_BufferObjectFormat;
+ mesa_format format = tObj->_BufferObjectFormat;
uint32_t brw_format = brw_format_for_mesa_format(format);
int texel_size = _mesa_get_format_bytes(format);
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
6 * 4, 32, surf_offset);
- (void) for_gather; /* no w/a to apply for this gen */
+ uint32_t tex_format = translate_tex_format(brw, mt->format,
+ sampler->sRGBDecode);
+
+ if (for_gather) {
+ /* Sandybridge's gather4 message is broken for integer formats.
+ * To work around this, we pretend the surface is UNORM for
+ * 8 or 16-bit formats, and emit shader instructions to recover
+ * the real INT/UINT value. For 32-bit formats, we pretend
+ * the surface is FLOAT, and simply reinterpret the resulting
+ * bits.
+ */
+ switch (tex_format) {
+ case BRW_SURFACEFORMAT_R8_SINT:
+ case BRW_SURFACEFORMAT_R8_UINT:
+ tex_format = BRW_SURFACEFORMAT_R8_UNORM;
+ break;
+
+ case BRW_SURFACEFORMAT_R16_SINT:
+ case BRW_SURFACEFORMAT_R16_UINT:
+ tex_format = BRW_SURFACEFORMAT_R16_UNORM;
+ break;
+
+ case BRW_SURFACEFORMAT_R32_SINT:
+ case BRW_SURFACEFORMAT_R32_UINT:
+ tex_format = BRW_SURFACEFORMAT_R32_FLOAT;
+ break;
+
+ default:
+ break;
+ }
+ }
surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
BRW_SURFACE_CUBEFACE_ENABLES |
- (translate_tex_format(brw,
- mt->format,
- tObj->DepthMode,
- sampler->sRGBDecode) <<
- BRW_SURFACE_FORMAT_SHIFT));
+ tex_format << BRW_SURFACE_FORMAT_SHIFT);
- surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */
+ surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
(mt->logical_width0 - 1) << BRW_SURFACE_WIDTH_SHIFT |
(mt->logical_height0 - 1) << BRW_SURFACE_HEIGHT_SHIFT);
- surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
+ surf[3] = (brw_get_surface_tiling_bits(mt->tiling) |
(mt->logical_depth0 - 1) << BRW_SURFACE_DEPTH_SHIFT |
- (intelObj->mt->region->pitch - 1) <<
- BRW_SURFACE_PITCH_SHIFT);
+ (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
- surf[4] = (brw_get_surface_num_multisamples(intelObj->mt->num_samples) |
+ surf[4] = (brw_get_surface_num_multisamples(mt->num_samples) |
SET_FIELD(tObj->BaseLevel - mt->first_level, BRW_SURFACE_MIN_LOD));
surf[5] = mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
/* Emit relocation to surface contents */
drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + 4,
- intelObj->mt->region->bo,
- surf[1] - intelObj->mt->region->bo->offset,
- I915_GEM_DOMAIN_SAMPLER, 0);
+ *surf_offset + 4,
+ mt->bo,
+ surf[1] - mt->bo->offset64,
+ I915_GEM_DOMAIN_SAMPLER, 0);
}
/**
BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
surface_format << BRW_SURFACE_FORMAT_SHIFT |
BRW_SURFACE_RC_READ_WRITE;
- surf[1] = bo->offset + offset_bytes; /* reloc */
+ surf[1] = bo->offset64 + offset_bytes; /* reloc */
surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
height << BRW_SURFACE_HEIGHT_SHIFT);
surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
struct brw_fragment_program *fp =
(struct brw_fragment_program *) brw->fragment_program;
struct gl_program_parameter_list *params = fp->program.Base.Parameters;
- const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
+ const int size = brw->wm.prog_data->base.nr_pull_params * sizeof(float);
const int surf_index =
brw->wm.prog_data->base.binding_table.pull_constants_start;
- float *constants;
unsigned int i;
_mesa_load_state_parameters(ctx, params);
/* CACHE_NEW_WM_PROG */
- if (brw->wm.prog_data->nr_pull_params == 0) {
- if (brw->wm.base.const_bo) {
- drm_intel_bo_unreference(brw->wm.base.const_bo);
- brw->wm.base.const_bo = NULL;
+ if (brw->wm.prog_data->base.nr_pull_params == 0) {
+ if (brw->wm.base.surf_offset[surf_index]) {
brw->wm.base.surf_offset[surf_index] = 0;
brw->state.dirty.brw |= BRW_NEW_SURFACES;
}
return;
}
- drm_intel_bo_unreference(brw->wm.base.const_bo);
- brw->wm.base.const_bo = drm_intel_bo_alloc(brw->bufmgr, "WM const bo",
- size, 64);
-
/* _NEW_PROGRAM_CONSTANTS */
- drm_intel_gem_bo_map_gtt(brw->wm.base.const_bo);
- constants = brw->wm.base.const_bo->virtual;
- for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
- constants[i] = *brw->wm.prog_data->pull_param[i];
+ drm_intel_bo *const_bo = NULL;
+ uint32_t const_offset;
+ float *constants = intel_upload_space(brw, size, 64,
+ &const_bo, &const_offset);
+ for (i = 0; i < brw->wm.prog_data->base.nr_pull_params; i++) {
+ constants[i] = *brw->wm.prog_data->base.pull_param[i];
}
- drm_intel_gem_bo_unmap_gtt(brw->wm.base.const_bo);
- brw_create_constant_surface(brw, brw->wm.base.const_bo, 0, size,
+ brw_create_constant_surface(brw, const_bo, const_offset, size,
&brw->wm.base.surf_offset[surf_index],
true);
+ drm_intel_bo_unreference(const_bo);
brw->state.dirty.brw |= BRW_NEW_SURFACES;
}
1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
}
- surf[1] = bo ? bo->offset : 0;
+ surf[1] = bo ? bo->offset64 : 0;
surf[2] = ((fb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(fb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
struct gl_context *ctx = &brw->ctx;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_mipmap_tree *mt = irb->mt;
- struct intel_region *region;
uint32_t *surf;
uint32_t tile_x, tile_y;
uint32_t format = 0;
/* _NEW_BUFFERS */
- gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
+ mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
uint32_t surf_index =
brw->wm.prog_data->binding_table.render_target_start + unit;
intel_miptree_used_for_rendering(irb->mt);
- region = irb->mt->region;
-
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
&brw->wm.base.surf_offset[surf_index]);
/* reloc */
surf[1] = (intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) +
- region->bo->offset);
+ mt->bo->offset64);
surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
- surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
- (region->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
+ surf[3] = (brw_get_surface_tiling_bits(mt->tiling) |
+ (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
drm_intel_bo_emit_reloc(brw->batch.bo,
brw->wm.base.surf_offset[surf_index] + 4,
- region->bo,
- surf[1] - region->bo->offset,
+ mt->bo,
+ surf[1] - mt->bo->offset64,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER);
}
for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
brw->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i],
- ctx->DrawBuffer->Layered, i);
+ ctx->DrawBuffer->MaxNumLayers > 0, i);
} else {
brw->vtbl.update_null_renderbuffer_surface(brw, i);
}
const unsigned unit = prog->SamplerUnits[s];
/* _NEW_TEXTURE */
- if (ctx->Texture.Unit[unit]._ReallyEnabled) {
+ if (ctx->Texture.Unit[unit]._Current) {
brw->vtbl.update_texture_surface(ctx, unit, surf_offset + s, for_gather);
}
}
brw_create_constant_surface(brw, bo, binding->Offset,
bo->size - binding->Offset,
&surf_offsets[i],
- shader->Type == GL_FRAGMENT_SHADER);
+ shader->Stage == MESA_SHADER_FRAGMENT);
}
if (shader->NumUniformBlocks)
{
struct gl_context *ctx = &brw->ctx;
/* _NEW_PROGRAM */
- struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram;
+ struct gl_shader_program *prog = ctx->_Shader->_CurrentFragmentProgram;
if (!prog)
return;
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