support branch and loop in pixel shader

[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_surface_state.c

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 51a56d67457598cc83fc8b2009a81ce7559da80f..d24c618a668b6ba950f10ae8175e414c37938b6b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -85,7 +85,8 @@ static GLuint translate_tex_format( GLuint mesa_format )
       return BRW_SURFACEFORMAT_L8A8_UNORM;
 
    case MESA_FORMAT_RGB888:
-      return BRW_SURFACEFORMAT_R8G8B8_UNORM;
+      assert(0);               /* not supported for sampling */
+      return BRW_SURFACEFORMAT_R8G8B8_UNORM;      
 
    case MESA_FORMAT_ARGB8888:
       return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
@@ -93,6 +94,15 @@ static GLuint translate_tex_format( GLuint mesa_format )
    case MESA_FORMAT_RGBA8888_REV:
       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
 
+   case MESA_FORMAT_RGB565:
+      return BRW_SURFACEFORMAT_B5G6R5_UNORM;
+
+   case MESA_FORMAT_ARGB1555:
+      return BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
+
+   case MESA_FORMAT_ARGB4444:
+      return BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
+
    case MESA_FORMAT_YCBCR_REV:
       return BRW_SURFACEFORMAT_YCRCB_NORMAL;
 
@@ -137,6 +147,7 @@ void brw_update_texture_surface( GLcontext *ctx,
     */
 /*    surf->ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
 
+   /* BRW_NEW_LOCK */
    surf->ss1.base_addr = bmBufferOffset(intel,
                                        intelObj->mt->region->buffer);
 
@@ -198,6 +209,7 @@ static void upload_wm_surfaces(struct brw_context *brw )
       surf.ss0.writedisable_blue =  !brw->attribs.Color->ColorMask[2];
       surf.ss0.writedisable_alpha = !brw->attribs.Color->ColorMask[3];
 
+      /* BRW_NEW_LOCK */
       surf.ss1.base_addr = bmBufferOffset(&brw->intel, region->buffer);
 
 
@@ -227,6 +239,12 @@ static void upload_wm_surfaces(struct brw_context *brw )
         brw->wm.bind.surf_ss_offset[i+1] = brw_cache_data( &brw->cache[BRW_SS_SURFACE], &surf );
         brw->wm.nr_surfaces = i+2;
       }
+      else if( texUnit->_ReallyEnabled &&
+              texUnit->_Current == intel->frame_buffer_texobj )
+      {
+        brw->wm.bind.surf_ss_offset[i+1] = brw->wm.bind.surf_ss_offset[0];
+        brw->wm.nr_surfaces = i+2;
+      }    
       else {
         brw->wm.bind.surf_ss_offset[i+1] = 0;
       }
@@ -240,7 +258,7 @@ const struct brw_tracked_state brw_wm_surfaces = {
    .dirty = {
       .mesa = _NEW_COLOR | _NEW_TEXTURE | _NEW_BUFFERS,
       .brw = (BRW_NEW_CONTEXT | 
-             BRW_NEW_FENCE),   /* required for bmBufferOffset */
+             BRW_NEW_LOCK),    /* required for bmBufferOffset */
       .cache = 0
    },
    .update = upload_wm_surfaces