aux_surf = &aux_surf_s;
if (mt->mcs_buf) {
- assert(mt->mcs_buf->offset == 0);
aux_bo = mt->mcs_buf->bo;
aux_offset = mt->mcs_buf->bo->offset64 + mt->mcs_buf->offset;
} else {
uint32_t *aux_addr = state + brw->isl_dev.ss.aux_addr_offset;
drm_intel_bo_emit_reloc(brw->batch.bo,
*surf_offset + brw->isl_dev.ss.aux_addr_offset,
- aux_bo, *aux_addr & 0xfff,
+ aux_bo, *aux_addr - aux_bo->offset64,
read_domains, write_domains);
}
}
if (!intel_miptree_is_lossless_compressed(brw, mt))
return true;
- if (isl_format_supports_lossless_compression(&brw->screen->devinfo,
- view->format))
+ if (isl_format_supports_ccs_e(&brw->screen->devinfo, view->format))
return true;
/* Logic elsewhere needs to take care to resolve the color buffer prior
/* Implement gen6 and gen7 gather work-around */
bool need_green_to_blue = false;
if (for_gather) {
- if (brw->gen == 7 && format == BRW_SURFACEFORMAT_R32G32_FLOAT) {
- format = BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
+ if (brw->gen == 7 && (format == ISL_FORMAT_R32G32_FLOAT ||
+ format == ISL_FORMAT_R32G32_SINT ||
+ format == ISL_FORMAT_R32G32_UINT)) {
+ format = ISL_FORMAT_R32G32_FLOAT_LD;
need_green_to_blue = brw->is_haswell;
} else if (brw->gen == 6) {
/* Sandybridge's gather4 message is broken for integer formats.
* bits.
*/
switch (format) {
- case BRW_SURFACEFORMAT_R8_SINT:
- case BRW_SURFACEFORMAT_R8_UINT:
- format = BRW_SURFACEFORMAT_R8_UNORM;
+ case ISL_FORMAT_R8_SINT:
+ case ISL_FORMAT_R8_UINT:
+ format = ISL_FORMAT_R8_UNORM;
break;
- case BRW_SURFACEFORMAT_R16_SINT:
- case BRW_SURFACEFORMAT_R16_UINT:
- format = BRW_SURFACEFORMAT_R16_UNORM;
+ case ISL_FORMAT_R16_SINT:
+ case ISL_FORMAT_R16_UINT:
+ format = ISL_FORMAT_R16_UNORM;
break;
- case BRW_SURFACEFORMAT_R32_SINT:
- case BRW_SURFACEFORMAT_R32_UINT:
- format = BRW_SURFACEFORMAT_R32_FLOAT;
+ case ISL_FORMAT_R32_SINT:
+ case ISL_FORMAT_R32_UINT:
+ format = ISL_FORMAT_R32_FLOAT;
break;
default:
} else {
mt = mt->stencil_mt;
}
- format = BRW_SURFACEFORMAT_R8_UINT;
+ format = ISL_FORMAT_R8_UINT;
} else if (brw->gen <= 7 && mt->format == MESA_FORMAT_S_UINT8) {
assert(mt->r8stencil_mt && !mt->r8stencil_needs_update);
mt = mt->r8stencil_mt;
- format = BRW_SURFACEFORMAT_R8_UINT;
+ format = ISL_FORMAT_R8_UINT;
}
const int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
bo = intel_bufferobj_buffer(brw, intel_obj, tObj->BufferOffset, size);
}
+ /* The ARB_texture_buffer_specification says:
+ *
+ * "The number of texels in the buffer texture's texel array is given by
+ *
+ * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
+ *
+ * where <buffer_size> is the size of the buffer object, in basic
+ * machine units and <components> and <base_type> are the element count
+ * and base data type for elements, as specified in Table X.1. The
+ * number of texels in the texel array is then clamped to the
+ * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
+ *
+ * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
+ * so that when ISL divides by stride to obtain the number of texels, that
+ * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
+ */
+ size = MIN2(size, ctx->Const.MaxTextureBufferSize * (unsigned) texel_size);
+
if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
_mesa_problem(NULL, "bad format %s for texture buffer\n",
_mesa_get_format_name(format));
uint32_t *out_offset)
{
brw_emit_buffer_surface_state(brw, out_offset, bo, offset,
- BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
+ ISL_FORMAT_R32G32B32A32_FLOAT,
size, 1, false);
}
* with helper invocations, which cannot write to the buffer.
*/
brw_emit_buffer_surface_state(brw, out_offset, bo, offset,
- BRW_SURFACEFORMAT_RAW,
+ ISL_FORMAT_RAW,
size, 1, true);
}
switch (num_vector_components) {
case 1:
- surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
+ surface_format = ISL_FORMAT_R32_FLOAT;
break;
case 2:
- surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
+ surface_format = ISL_FORMAT_R32G32_FLOAT;
break;
case 3:
- surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
+ surface_format = ISL_FORMAT_R32G32B32_FLOAT;
break;
case 4:
- surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
+ surface_format = ISL_FORMAT_R32G32B32A32_FLOAT;
break;
default:
unreachable("Invalid vector size for transform feedback output");
}
surf[0] = (surface_type << BRW_SURFACE_TYPE_SHIFT |
- BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
+ ISL_FORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
if (brw->gen < 6) {
surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
{
struct gl_context *ctx = &brw->ctx;
/* _NEW_PROGRAM */
- struct gl_shader_program *prog = ctx->_Shader->_CurrentFragmentProgram;
-
- if (!prog || !prog->_LinkedShaders[MESA_SHADER_FRAGMENT])
- return;
+ struct gl_program *prog = ctx->_Shader->_CurrentFragmentProgram;
/* BRW_NEW_FS_PROG_DATA */
- brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT]->Program,
- &brw->wm.base, brw->wm.base.prog_data);
+ brw_upload_ubo_surfaces(brw, prog, &brw->wm.base, brw->wm.base.prog_data);
}
const struct brw_tracked_state brw_wm_ubo_surfaces = {
{
struct gl_context *ctx = &brw->ctx;
/* _NEW_PROGRAM */
- struct gl_shader_program *prog =
+ struct gl_program *prog =
ctx->_Shader->CurrentProgram[MESA_SHADER_COMPUTE];
- if (!prog || !prog->_LinkedShaders[MESA_SHADER_COMPUTE])
- return;
-
/* BRW_NEW_CS_PROG_DATA */
- brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_COMPUTE]->Program,
- &brw->cs.base, brw->cs.base.prog_data);
+ brw_upload_ubo_surfaces(brw, prog, &brw->cs.base, brw->cs.base.prog_data);
}
const struct brw_tracked_state brw_cs_ubo_surfaces = {
brw, intel_bo, binding->Offset, intel_bo->Base.Size - binding->Offset);
brw_emit_buffer_surface_state(brw, &surf_offsets[i], bo,
- binding->Offset, BRW_SURFACEFORMAT_RAW,
+ binding->Offset, ISL_FORMAT_RAW,
bo->size - binding->Offset, 1, true);
}
/* The hardware doesn't actually support a typed format that we can use
* so we have to fall back to untyped read/write messages.
*/
- return BRW_SURFACEFORMAT_RAW;
+ return ISL_FORMAT_RAW;
}
}
if (obj->Target == GL_TEXTURE_BUFFER) {
struct intel_buffer_object *intel_obj =
intel_buffer_object(obj->BufferObject);
- const unsigned texel_size = (format == BRW_SURFACEFORMAT_RAW ? 1 :
+ const unsigned texel_size = (format == ISL_FORMAT_RAW ? 1 :
_mesa_get_format_bytes(u->_ActualFormat));
brw_emit_buffer_surface_state(
struct intel_texture_object *intel_obj = intel_texture_object(obj);
struct intel_mipmap_tree *mt = intel_obj->mt;
- if (format == BRW_SURFACEFORMAT_RAW) {
+ if (format == ISL_FORMAT_RAW) {
brw_emit_buffer_surface_state(
brw, surf_offset, mt->bo, mt->offset,
format, mt->bo->size - mt->offset, 1 /* pitch */,
{
struct gl_context *ctx = &brw->ctx;
/* _NEW_PROGRAM */
- struct gl_shader_program *prog =
+ struct gl_program *prog =
ctx->_Shader->CurrentProgram[MESA_SHADER_COMPUTE];
/* BRW_NEW_CS_PROG_DATA */
const struct brw_cs_prog_data *cs_prog_data =
brw_emit_buffer_surface_state(brw, surf_offset,
bo, bo_offset,
- BRW_SURFACEFORMAT_RAW,
+ ISL_FORMAT_RAW,
3 * sizeof(GLuint), 1, true);
brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
}
projects / mesa.git / blobdiff