i965/nir/vec4: Prepare source and destination registers for ALU operations

[mesa.git] / src / mesa / drivers / dri / i965 / gen6_blorp.cpp

diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 14e073b237f29be60f3fc8801f0b9bbc1074580c..54c4a6dfdd87bdc9b8acb61e6b20bd9570fe43a0 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -246,21 +246,21 @@ gen6_blorp_emit_blend_state(struct brw_context *brw,
 {
    uint32_t cc_blend_state_offset;
 
+   assume(params->num_draw_buffers);
+
+   const unsigned size = params->num_draw_buffers *
+                         sizeof(struct gen6_blend_state);
    struct gen6_blend_state *blend = (struct gen6_blend_state *)
-      brw_state_batch(brw, AUB_TRACE_BLEND_STATE,
-                      sizeof(struct gen6_blend_state), 64,
+      brw_state_batch(brw, AUB_TRACE_BLEND_STATE, size, 64,
                       &cc_blend_state_offset);
 
-   memset(blend, 0, sizeof(*blend));
-
-   blend->blend1.pre_blend_clamp_enable = 1;
-   blend->blend1.post_blend_clamp_enable = 1;
-   blend->blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT;
+   memset(blend, 0, size);
 
-   blend->blend1.write_disable_r = params->color_write_disable[0];
-   blend->blend1.write_disable_g = params->color_write_disable[1];
-   blend->blend1.write_disable_b = params->color_write_disable[2];
-   blend->blend1.write_disable_a = params->color_write_disable[3];
+   for (unsigned i = 0; i < params->num_draw_buffers; ++i) {
+      blend[i].blend1.pre_blend_clamp_enable = 1;
+      blend[i].blend1.post_blend_clamp_enable = 1;
+      blend[i].blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT;
+   }
 
    return cc_blend_state_offset;
 }
@@ -268,8 +268,7 @@ gen6_blorp_emit_blend_state(struct brw_context *brw,
 
 /* CC_STATE */
 uint32_t
-gen6_blorp_emit_cc_state(struct brw_context *brw,
-                         const brw_blorp_params *params)
+gen6_blorp_emit_cc_state(struct brw_context *brw)
 {
    uint32_t cc_state_offset;
 
@@ -431,7 +430,6 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
 /* BINDING_TABLE.  See brw_wm_binding_table(). */
 uint32_t
 gen6_blorp_emit_binding_table(struct brw_context *brw,
-                              const brw_blorp_params *params,
                               uint32_t wm_surf_offset_renderbuffer,
                               uint32_t wm_surf_offset_texture)
 {
@@ -502,7 +500,6 @@ gen6_blorp_emit_sampler_state(struct brw_context *brw,
  */
 static void
 gen6_blorp_emit_sampler_state_pointers(struct brw_context *brw,
-                                       const brw_blorp_params *params,
                                        uint32_t sampler_offset)
 {
    BEGIN_BATCH(4);
@@ -602,8 +599,7 @@ gen6_blorp_emit_gs_disable(struct brw_context *brw,
  * output, but does spare a few electrons.
  */
 void
-gen6_blorp_emit_clip_disable(struct brw_context *brw,
-                             const brw_blorp_params *params)
+gen6_blorp_emit_clip_disable(struct brw_context *brw)
 {
    BEGIN_BATCH(4);
    OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2));
@@ -638,9 +634,10 @@ gen6_blorp_emit_sf_config(struct brw_context *brw,
 {
    BEGIN_BATCH(20);
    OUT_BATCH(_3DSTATE_SF << 16 | (20 - 2));
-   OUT_BATCH((1 - 1) << GEN6_SF_NUM_OUTPUTS_SHIFT | /* only position */
+   OUT_BATCH(params->num_varyings << GEN6_SF_NUM_OUTPUTS_SHIFT |
              1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
-             0 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT);
+             BRW_SF_URB_ENTRY_READ_OFFSET <<
+                GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT);
    OUT_BATCH(0); /* dw2 */
    OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
    for (int i = 0; i < 16; ++i)
@@ -767,7 +764,6 @@ gen6_blorp_emit_constant_ps_disable(struct brw_context *brw,
  */
 static void
 gen6_blorp_emit_binding_table_pointers(struct brw_context *brw,
-                                       const brw_blorp_params *params,
                                        uint32_t wm_bind_bo_offset)
 {
    BEGIN_BATCH(4);
@@ -825,7 +821,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
 
    /* 3DSTATE_DEPTH_BUFFER */
    {
-      intel_emit_depth_stall_flushes(brw);
+      brw_emit_depth_stall_flushes(brw);
 
       BEGIN_BATCH(7);
       /* 3DSTATE_DEPTH_BUFFER dw0 */
@@ -900,7 +896,7 @@ static void
 gen6_blorp_emit_depth_disable(struct brw_context *brw,
                               const brw_blorp_params *params)
 {
-   intel_emit_depth_stall_flushes(brw);
+   brw_emit_depth_stall_flushes(brw);
 
    BEGIN_BATCH(7);
    OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
@@ -954,8 +950,8 @@ gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
    BEGIN_BATCH(4);
    OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
    OUT_BATCH(0);
-   OUT_BATCH(((params->x1 - 1) & 0xffff) |
-             ((params->y1 - 1) << 16));
+   OUT_BATCH(((MAX2(params->x1, params->x0) - 1) & 0xffff) |
+             ((MAX2(params->y1, params->y0) - 1) << 16));
    OUT_BATCH(0);
    ADVANCE_BATCH();
 }
@@ -996,7 +992,7 @@ gen6_blorp_emit_primitive(struct brw_context *brw,
              GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL);
    OUT_BATCH(3); /* vertex count per instance */
    OUT_BATCH(0);
-   OUT_BATCH(1); /* instance count */
+   OUT_BATCH(params->num_layers); /* instance count */
    OUT_BATCH(0);
    OUT_BATCH(0);
    ADVANCE_BATCH();
@@ -1025,7 +1021,7 @@ gen6_blorp_exec(struct brw_context *brw,
    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 
    /* Emit workaround flushes when we switch from drawing to blorping. */
-   intel_emit_post_sync_nonzero_flush(brw);
+   brw_emit_post_sync_nonzero_flush(brw);
 
    gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
    gen6_emit_3dstate_sample_mask(brw,
@@ -1036,7 +1032,7 @@ gen6_blorp_exec(struct brw_context *brw,
    gen6_blorp_emit_urb_config(brw, params);
    if (params->use_wm_prog) {
       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
-      cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
+      cc_state_offset = gen6_blorp_emit_cc_state(brw);
    }
    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
    gen6_blorp_emit_cc_state_pointers(brw, params, cc_blend_state_offset,
@@ -1057,17 +1053,16 @@ gen6_blorp_exec(struct brw_context *brw,
                                           I915_GEM_DOMAIN_SAMPLER, 0);
       }
       wm_bind_bo_offset =
-         gen6_blorp_emit_binding_table(brw, params,
+         gen6_blorp_emit_binding_table(brw,
                                        wm_surf_offset_renderbuffer,
                                        wm_surf_offset_texture);
       sampler_offset =
          gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
-                                                
-      gen6_blorp_emit_sampler_state_pointers(brw, params, sampler_offset);
+      gen6_blorp_emit_sampler_state_pointers(brw, sampler_offset);
    }
    gen6_blorp_emit_vs_disable(brw, params);
    gen6_blorp_emit_gs_disable(brw, params);
-   gen6_blorp_emit_clip_disable(brw, params);
+   gen6_blorp_emit_clip_disable(brw);
    gen6_blorp_emit_sf_config(brw, params);
    if (params->use_wm_prog)
       gen6_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
@@ -1075,7 +1070,7 @@ gen6_blorp_exec(struct brw_context *brw,
       gen6_blorp_emit_constant_ps_disable(brw, params);
    gen6_blorp_emit_wm_config(brw, params, prog_offset, prog_data);
    if (params->use_wm_prog)
-      gen6_blorp_emit_binding_table_pointers(brw, params, wm_bind_bo_offset);
+      gen6_blorp_emit_binding_table_pointers(brw, wm_bind_bo_offset);
    gen6_blorp_emit_viewport_state(brw, params);
 
    if (params->depth.mt)