gen6_blorp_emit_batch_head(struct brw_context *brw,
const brw_blorp_params *params)
{
- struct gl_context *ctx = &brw->ctx;
-
/* To ensure that the batch contains only the resolve, flush the batch
* before beginning and after finishing emitting the resolve packets.
*/
- intel_flush(ctx);
+ intel_batchbuffer_flush(brw);
}
gen6_blorp_emit_state_base_address(struct brw_context *brw,
const brw_blorp_params *params)
{
+ uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0;
+
BEGIN_BATCH(10);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
- OUT_BATCH(1); /* GeneralStateBaseAddressModifyEnable */
+ OUT_BATCH(mocs << 8 | /* GeneralStateMemoryObjectControlState */
+ mocs << 4 | /* StatelessDataPortAccessMemoryObjectControlState */
+ 1); /* GeneralStateBaseAddressModifyEnable */
+
/* SurfaceStateBaseAddress */
OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
/* DynamicStateBaseAddress */
if (brw->gen >= 7)
dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
+ if (brw->gen == 7)
+ dw0 |= GEN7_MOCS_L3 << 16;
+
BEGIN_BATCH(batch_length);
OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2));
OUT_BATCH(dw0);
const brw_blorp_params *params)
{
if (brw->gen == 6) {
- /* From the BSpec, Volume 2a, Part 3 "Vertex Shader", Section
+ /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
* 3DSTATE_VS, Dword 5.0 "VS Function Enable":
*
* [DevSNB] A pipeline flush must be programmed prior to a
uint32_t dw2, dw4, dw5, dw6;
/* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
- * nonzero to prevent the GPU from hanging. See the valid ranges in the
- * BSpec, Volume 2a.11 Windower, Section 3DSTATE_WM, Dword 5.25:31
- * "Maximum Number Of Threads".
+ * nonzero to prevent the GPU from hanging. While the documentation doesn't
+ * mention this explicitly, it notes that the valid range for the field is
+ * [1,39] = [2,40] threads, which excludes zero.
*
* To be safe (and to minimize extraneous code) we go ahead and fully
* configure the WM state whether or not there is a WM program.
gen6_blorp_emit_depth_disable(struct brw_context *brw,
const brw_blorp_params *params)
{
+ intel_emit_post_sync_nonzero_flush(brw);
+ intel_emit_depth_stall_flushes(brw);
+
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |