i965/vec4: Don't lose the force_writemask_all flag during CSE.

[mesa.git] / src / mesa / drivers / dri / i965 / gen6_cc.c

diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index b4a570960c8ad5ff7bf80920ec82a439a500068d..2bfa271b5271f1623a1767abea02300d613e6605 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -39,8 +39,7 @@ static void
 gen6_upload_blend_state(struct brw_context *brw)
 {
    bool is_buffer_zero_integer_format = false;
-   struct intel_context *intel = &brw->intel;
-   struct gl_context *ctx = &brw->intel.ctx;
+   struct gl_context *ctx = &brw->ctx;
    struct gen6_blend_state *blend;
    int b;
    int nr_draw_buffers = ctx->DrawBuffer->_NumColorDrawBuffers;
@@ -216,7 +215,7 @@ gen6_upload_blend_state(struct brw_context *brw)
            blend[b].blend1.alpha_to_one =
               ctx->Multisample._Enabled && ctx->Multisample.SampleAlphaToOne;
 
-         blend[b].blend1.alpha_to_coverage_dither = (brw->intel.gen >= 7);
+         blend[b].blend1.alpha_to_coverage_dither = (brw->gen >= 7);
       }
       else {
          blend[b].blend1.alpha_to_coverage = false;
@@ -225,7 +224,7 @@ gen6_upload_blend_state(struct brw_context *brw)
    }
 
    /* Point the GPU at the new indirect state. */
-   if (intel->gen == 6) {
+   if (brw->gen == 6) {
       BEGIN_BATCH(4);
       OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
       OUT_BATCH(brw->cc.blend_state_offset | 1);
@@ -242,11 +241,11 @@ gen6_upload_blend_state(struct brw_context *brw)
 
 const struct brw_tracked_state gen6_blend_state = {
    .dirty = {
-      .mesa = (_NEW_COLOR |
-               _NEW_BUFFERS |
-               _NEW_MULTISAMPLE),
-      .brw = BRW_NEW_BATCH | BRW_NEW_STATE_BASE_ADDRESS,
-      .cache = 0,
+      .mesa = _NEW_BUFFERS |
+              _NEW_COLOR |
+              _NEW_MULTISAMPLE,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_STATE_BASE_ADDRESS,
    },
    .emit = gen6_upload_blend_state,
 };
@@ -254,8 +253,7 @@ const struct brw_tracked_state gen6_blend_state = {
 static void
 gen6_upload_color_calc_state(struct brw_context *brw)
 {
-   struct gl_context *ctx = &brw->intel.ctx;
-   struct intel_context *intel = &brw->intel;
+   struct gl_context *ctx = &brw->ctx;
    struct gen6_color_calc_state *cc;
 
    cc = brw_state_batch(brw, AUB_TRACE_CC_STATE,
@@ -266,9 +264,12 @@ gen6_upload_color_calc_state(struct brw_context *brw)
    cc->cc0.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8;
    UNCLAMPED_FLOAT_TO_UBYTE(cc->cc1.alpha_ref_fi.ui, ctx->Color.AlphaRef);
 
-   /* _NEW_STENCIL */
-   cc->cc0.stencil_ref = _mesa_get_stencil_ref(ctx, 0);
-   cc->cc0.bf_stencil_ref = _mesa_get_stencil_ref(ctx, ctx->Stencil._BackFace);
+   if (brw->gen < 9) {
+      /* _NEW_STENCIL */
+      cc->cc0.stencil_ref = _mesa_get_stencil_ref(ctx, 0);
+      cc->cc0.bf_stencil_ref =
+         _mesa_get_stencil_ref(ctx, ctx->Stencil._BackFace);
+   }
 
    /* _NEW_COLOR */
    cc->constant_r = ctx->Color.BlendColorUnclamped[0];
@@ -277,7 +278,7 @@ gen6_upload_color_calc_state(struct brw_context *brw)
    cc->constant_a = ctx->Color.BlendColorUnclamped[3];
 
    /* Point the GPU at the new indirect state. */
-   if (intel->gen == 6) {
+   if (brw->gen == 6) {
       BEGIN_BATCH(4);
       OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
       OUT_BATCH(0);
@@ -294,9 +295,10 @@ gen6_upload_color_calc_state(struct brw_context *brw)
 
 const struct brw_tracked_state gen6_color_calc_state = {
    .dirty = {
-      .mesa = _NEW_COLOR | _NEW_STENCIL,
-      .brw = BRW_NEW_BATCH | BRW_NEW_STATE_BASE_ADDRESS,
-      .cache = 0,
+      .mesa = _NEW_COLOR |
+              _NEW_STENCIL,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_STATE_BASE_ADDRESS,
    },
    .emit = gen6_upload_color_calc_state,
 };