gen6_upload_blend_state(struct brw_context *brw)
{
bool is_buffer_zero_integer_format = false;
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &brw->intel.ctx;
+ struct gl_context *ctx = &brw->ctx;
struct gen6_blend_state *blend;
int b;
int nr_draw_buffers = ctx->DrawBuffer->_NumColorDrawBuffers;
blend[b].blend1.alpha_to_one =
ctx->Multisample._Enabled && ctx->Multisample.SampleAlphaToOne;
- blend[b].blend1.alpha_to_coverage_dither = (brw->intel.gen >= 7);
+ blend[b].blend1.alpha_to_coverage_dither = (brw->gen >= 7);
}
else {
blend[b].blend1.alpha_to_coverage = false;
}
/* Point the GPU at the new indirect state. */
- if (intel->gen == 6) {
+ if (brw->gen == 6) {
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
OUT_BATCH(brw->cc.blend_state_offset | 1);
static void
gen6_upload_color_calc_state(struct brw_context *brw)
{
- struct gl_context *ctx = &brw->intel.ctx;
- struct intel_context *intel = &brw->intel;
+ struct gl_context *ctx = &brw->ctx;
struct gen6_color_calc_state *cc;
cc = brw_state_batch(brw, AUB_TRACE_CC_STATE,
cc->constant_a = ctx->Color.BlendColorUnclamped[3];
/* Point the GPU at the new indirect state. */
- if (intel->gen == 6) {
+ if (brw->gen == 6) {
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
OUT_BATCH(0);
},
.emit = gen6_upload_color_calc_state,
};
-
-static void upload_cc_state_pointers(struct brw_context *brw)
-{
- struct intel_context *intel = &brw->intel;
-
- BEGIN_BATCH(4);
- OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
- OUT_BATCH(0);
- OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
- OUT_BATCH(0);
- ADVANCE_BATCH();
-}
-
-const struct brw_tracked_state gen6_cc_state_pointers = {
- .dirty = {
- .mesa = 0,
- .brw = (BRW_NEW_BATCH |
- BRW_NEW_STATE_BASE_ADDRESS),
- .cache = CACHE_NEW_DEPTH_STENCIL_STATE
- },
- .emit = upload_cc_state_pointers,
-};