i965/vs: Add a function for how many MRFs get written as part of a SEND.

[mesa.git] / src / mesa / drivers / dri / i965 / gen6_cc.c

diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index 294d5a5e6446c8ca0f27c75d305ed168697efcf4..b8047d5e9f06e8d359bc3838bb29d2ccee417d15 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -51,13 +51,14 @@ prepare_blend_state(struct brw_context *brw)
       nr_draw_buffers = 1;
 
    size = sizeof(*blend) * nr_draw_buffers;
-   blend = brw_state_batch(brw, size, 64, &brw->cc.blend_state_offset);
+   blend = brw_state_batch(brw, AUB_TRACE_BLEND_STATE,
+                          size, 64, &brw->cc.blend_state_offset);
 
    memset(blend, 0, size);
 
    for (b = 0; b < nr_draw_buffers; b++) {
       /* _NEW_COLOR */
-      if (ctx->Color._LogicOpEnabled) {
+      if (ctx->Color.ColorLogicOpEnabled) {
         struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[b];
         /* _NEW_BUFFERS */
         /* Floating point RTs should have no effect from LogicOp,
@@ -139,7 +140,8 @@ gen6_prepare_color_calc_state(struct brw_context *brw)
    struct gl_context *ctx = &brw->intel.ctx;
    struct gen6_color_calc_state *cc;
 
-   cc = brw_state_batch(brw, sizeof(*cc), 64, &brw->cc.state_offset);
+   cc = brw_state_batch(brw, AUB_TRACE_CC_STATE,
+                       sizeof(*cc), 64, &brw->cc.state_offset);
    memset(cc, 0, sizeof(*cc));
 
    /* _NEW_COLOR */