i965: Implement GenerateMipmap directly, rather than using Meta.

[mesa.git] / src / mesa / drivers / dri / i965 / gen6_depth_state.c

diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index 1a29860580dfb67fd21f377b1c1416e32e40ef5a..3a66b42fec1fac9eb99f7d8207f87373918c586f 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -91,7 +91,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
       break;
    case GL_TEXTURE_3D:
       assert(mt);
-      depth = MAX2(mt->logical_depth0, 1);
+      depth = mt->surf.logical_level0_px.depth;
       /* fallthrough */
    default:
       surftype = translate_tex_target(gl_target);
@@ -103,8 +103,8 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
    lod = irb ? irb->mt_level - irb->mt->first_level : 0;
 
    if (mt) {
-      width = mt->logical_width0;
-      height = mt->logical_height0;
+      width = mt->surf.logical_level0_px.width;
+      height = mt->surf.logical_level0_px.height;
    }
 
    BEGIN_BATCH(7);
@@ -112,20 +112,17 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
    OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 
    /* 3DSTATE_DEPTH_BUFFER dw1 */
-   OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
+   OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
              (depthbuffer_format << 18) |
              ((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable */
              ((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */
              (BRW_TILEWALK_YMAJOR << 26) |
-             ((depth_mt ? depth_mt->tiling != I915_TILING_NONE : 1)
-              << 27) |
+             (1 << 27) |
              (surftype << 29));
 
    /* 3DSTATE_DEPTH_BUFFER dw2 */
    if (depth_mt) {
-      OUT_RELOC(depth_mt->bo,
-               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-               0);
+      OUT_RELOC(depth_mt->bo, RELOC_WRITE, 0);
    } else {
       OUT_BATCH(0);
    }
@@ -161,23 +158,15 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
       /* Emit hiz buffer. */
       if (hiz) {
          assert(depth_mt);
-         struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_buf->mt;
-         uint32_t offset = 0;
 
-         if (hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
-            offset = intel_miptree_get_aligned_offset(
-                        hiz_mt,
-                        hiz_mt->level[lod].level_x,
-                        hiz_mt->level[lod].level_y,
-                        false);
-         }
+         uint32_t offset;
+         isl_surf_get_image_offset_B_tile_sa(&depth_mt->hiz_buf->surf,
+                                             lod, 0, 0, &offset, NULL, NULL);
 
         BEGIN_BATCH(3);
         OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
-        OUT_BATCH(hiz_mt->pitch - 1);
-        OUT_RELOC(hiz_mt->bo,
-                  I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-                  offset);
+        OUT_BATCH(depth_mt->hiz_buf->surf.row_pitch - 1);
+        OUT_RELOC(depth_mt->hiz_buf->bo, RELOC_WRITE, offset);
         ADVANCE_BATCH();
       } else {
         BEGIN_BATCH(3);
@@ -189,37 +178,17 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
 
       /* Emit stencil buffer. */
       if (separate_stencil) {
-         uint32_t offset = 0;
-
-         if (stencil_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
-            if (stencil_mt->format == MESA_FORMAT_S_UINT8) {
-               /* Note: we can't compute the stencil offset using
-                * intel_region_get_aligned_offset(), because stencil_region
-                * claims that the region is untiled even though it's W tiled.
-                */
-               offset =
-                  stencil_mt->level[lod].level_y * stencil_mt->pitch +
-                  stencil_mt->level[lod].level_x * 64;
-            } else {
-               offset = intel_miptree_get_aligned_offset(
-                           stencil_mt,
-                           stencil_mt->level[lod].level_x,
-                           stencil_mt->level[lod].level_y,
-                           false);
-            }
-         }
+         assert(stencil_mt->format == MESA_FORMAT_S_UINT8);
+         assert(stencil_mt->surf.size > 0);
+
+         uint32_t offset;
+         isl_surf_get_image_offset_B_tile_sa(&stencil_mt->surf,
+                                             lod, 0, 0, &offset, NULL, NULL);
 
         BEGIN_BATCH(3);
         OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
-         /* The stencil buffer has quirky pitch requirements.  From Vol 2a,
-          * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
-          *    The pitch must be set to 2x the value computed based on width, as
-          *    the stencil buffer is stored with two rows interleaved.
-          */
-        OUT_BATCH(2 * stencil_mt->pitch - 1);
-        OUT_RELOC(stencil_mt->bo,
-                  I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-                  offset);
+        OUT_BATCH(stencil_mt->surf.row_pitch - 1);
+        OUT_RELOC(stencil_mt->bo, RELOC_WRITE, offset);
         ADVANCE_BATCH();
       } else {
         BEGIN_BATCH(3);
@@ -242,6 +211,11 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
    OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 |
              GEN5_DEPTH_CLEAR_VALID |
              (2 - 2));
-   OUT_BATCH(depth_mt ? depth_mt->depth_clear_value : 0);
+   if (depth_mt) {
+      OUT_BATCH(brw_convert_depth_value(depth_mt->format,
+                                        depth_mt->fast_clear_color.f32[0]));
+   } else {
+      OUT_BATCH(0);
+   }
    ADVANCE_BATCH();
 }