i965: Rewrite the HiZ op

[mesa.git] / src / mesa / drivers / dri / i965 / gen6_depthstencil.c

diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
index d9f686a259e0a9925151d668b1bbb81af1fe82ad..4ea517ff336b69d376d6f61f51fdc1d80aa59961 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
+++ b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
@@ -82,11 +82,7 @@ gen6_upload_depth_stencil_state(struct brw_context *brw)
    }
 
    /* _NEW_DEPTH */
-   if ((ctx->Depth.Test || brw->hiz.op) && depth_irb) {
-      assert(brw->hiz.op != BRW_HIZ_OP_DEPTH_RESOLVE || ctx->Depth.Test);
-      assert(brw->hiz.op != BRW_HIZ_OP_HIZ_RESOLVE   || !ctx->Depth.Test);
-      assert(brw->hiz.op != BRW_HIZ_OP_DEPTH_CLEAR   || !ctx->Depth.Test);
-
+   if (ctx->Depth.Test && depth_irb) {
       ds->ds2.depth_test_enable = ctx->Depth.Test;
       ds->ds2.depth_test_func = intel_translate_compare_func(ctx->Depth.Func);
       ds->ds2.depth_write_enable = ctx->Depth.Mask;
@@ -98,8 +94,7 @@ gen6_upload_depth_stencil_state(struct brw_context *brw)
 const struct brw_tracked_state gen6_depth_stencil_state = {
    .dirty = {
       .mesa = _NEW_DEPTH | _NEW_STENCIL | _NEW_BUFFERS,
-      .brw  = (BRW_NEW_BATCH |
-              BRW_NEW_HIZ),
+      .brw  = BRW_NEW_BATCH,
       .cache = 0,
    },
    .emit = gen6_upload_depth_stencil_state,