i965/nir/vec4: Implement single-element "mov" operations

[mesa.git] / src / mesa / drivers / dri / i965 / gen6_depthstencil.c

diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
index a8dbc62ab4fee15b8a23b5e91c19c6670de2124c..2c625c98403defea2e440060e4079bd89172313a 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
+++ b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
@@ -34,8 +34,7 @@
 static void
 gen6_upload_depth_stencil_state(struct brw_context *brw)
 {
-   struct gl_context *ctx = &brw->intel.ctx;
-   struct intel_context *intel = &brw->intel;
+   struct gl_context *ctx = &brw->ctx;
    struct gen6_depth_stencil_state *ds;
    struct intel_renderbuffer *depth_irb;
 
@@ -47,7 +46,7 @@ gen6_upload_depth_stencil_state(struct brw_context *brw)
                        &brw->cc.depth_stencil_state_offset);
    memset(ds, 0, sizeof(*ds));
 
-   /* _NEW_STENCIL */
+   /* _NEW_STENCIL | _NEW_BUFFERS */
    if (ctx->Stencil._Enabled) {
       int back = ctx->Stencil._BackFace;
 
@@ -88,7 +87,7 @@ gen6_upload_depth_stencil_state(struct brw_context *brw)
    }
 
    /* Point the GPU at the new indirect state. */
-   if (intel->gen == 6) {
+   if (brw->gen == 6) {
       BEGIN_BATCH(4);
       OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
       OUT_BATCH(0);
@@ -105,9 +104,11 @@ gen6_upload_depth_stencil_state(struct brw_context *brw)
 
 const struct brw_tracked_state gen6_depth_stencil_state = {
    .dirty = {
-      .mesa = _NEW_DEPTH | _NEW_STENCIL | _NEW_BUFFERS,
-      .brw  = BRW_NEW_BATCH | BRW_NEW_STATE_BASE_ADDRESS,
-      .cache = 0,
+      .mesa = _NEW_BUFFERS |
+              _NEW_DEPTH |
+              _NEW_STENCIL,
+      .brw  = BRW_NEW_BATCH |
+              BRW_NEW_STATE_BASE_ADDRESS,
    },
    .emit = gen6_upload_depth_stencil_state,
 };