i965: Delete intel_context entirely.

[mesa.git] / src / mesa / drivers / dri / i965 / gen6_depthstencil.c

diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
index 5d14147db3dbe1faca4c74aa31479d13c95d1c95..7b06c1e90f90984934a4c31a7da8c043b57ac466 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
+++ b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
@@ -25,21 +25,28 @@
  *
  */
 
+#include "intel_batchbuffer.h"
+#include "intel_fbo.h"
 #include "brw_context.h"
+#include "brw_defines.h"
 #include "brw_state.h"
 
 static void
-gen6_prepare_depth_stencil_state(struct brw_context *brw)
+gen6_upload_depth_stencil_state(struct brw_context *brw)
 {
-   struct gl_context *ctx = &brw->intel.ctx;
+   struct gl_context *ctx = &brw->ctx;
    struct gen6_depth_stencil_state *ds;
+   struct intel_renderbuffer *depth_irb;
+
+   /* _NEW_BUFFERS */
+   depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
 
    ds = brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE,
                        sizeof(*ds), 64,
                        &brw->cc.depth_stencil_state_offset);
    memset(ds, 0, sizeof(*ds));
 
-   /* _NEW_STENCIL */
+   /* _NEW_STENCIL | _NEW_BUFFERS */
    if (ctx->Stencil._Enabled) {
       int back = ctx->Stencil._BackFace;
 
@@ -69,28 +76,37 @@ gen6_prepare_depth_stencil_state(struct brw_context *brw)
         ds->ds1.bf_stencil_test_mask = ctx->Stencil.ValueMask[back];
       }
 
-      /* Not really sure about this:
-       */
-      if (ctx->Stencil.WriteMask[0] ||
-         (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back]))
-        ds->ds0.stencil_write_enable = 1;
+      ds->ds0.stencil_write_enable = ctx->Stencil._WriteEnabled;
    }
 
    /* _NEW_DEPTH */
-   if (ctx->Depth.Test) {
-      ds->ds2.depth_test_enable = 1;
+   if (ctx->Depth.Test && depth_irb) {
+      ds->ds2.depth_test_enable = ctx->Depth.Test;
       ds->ds2.depth_test_func = intel_translate_compare_func(ctx->Depth.Func);
       ds->ds2.depth_write_enable = ctx->Depth.Mask;
    }
 
-   brw->state.dirty.cache |= CACHE_NEW_DEPTH_STENCIL_STATE;
+   /* Point the GPU at the new indirect state. */
+   if (brw->gen == 6) {
+      BEGIN_BATCH(4);
+      OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
+      OUT_BATCH(0);
+      OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
+      OUT_BATCH(0);
+      ADVANCE_BATCH();
+   } else {
+      BEGIN_BATCH(2);
+      OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
+      OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
+      ADVANCE_BATCH();
+   }
 }
 
 const struct brw_tracked_state gen6_depth_stencil_state = {
    .dirty = {
-      .mesa = _NEW_DEPTH | _NEW_STENCIL,
-      .brw = BRW_NEW_BATCH,
+      .mesa = _NEW_DEPTH | _NEW_STENCIL | _NEW_BUFFERS,
+      .brw  = BRW_NEW_BATCH | BRW_NEW_STATE_BASE_ADDRESS,
       .cache = 0,
    },
-   .prepare = gen6_prepare_depth_stencil_state,
+   .emit = gen6_upload_depth_stencil_state,
 };