mesa: add/update comments in _mesa_copy_buffer_subdata()
[mesa.git] / src / mesa / drivers / dri / i965 / gen6_depthstencil.c
index 5d14147db3dbe1faca4c74aa31479d13c95d1c95..c601a8fb13e29fc2ee2c6d7847431b2fee31e3fe 100644 (file)
  *
  */
 
+#include "intel_fbo.h"
 #include "brw_context.h"
 #include "brw_state.h"
 
 static void
-gen6_prepare_depth_stencil_state(struct brw_context *brw)
+gen6_upload_depth_stencil_state(struct brw_context *brw)
 {
    struct gl_context *ctx = &brw->intel.ctx;
    struct gen6_depth_stencil_state *ds;
+   struct intel_renderbuffer *depth_irb;
+
+   /* _NEW_BUFFERS */
+   depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
 
    ds = brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE,
                        sizeof(*ds), 64,
@@ -77,8 +82,12 @@ gen6_prepare_depth_stencil_state(struct brw_context *brw)
    }
 
    /* _NEW_DEPTH */
-   if (ctx->Depth.Test) {
-      ds->ds2.depth_test_enable = 1;
+   if ((ctx->Depth.Test || brw->hiz.op) && depth_irb) {
+      assert(brw->hiz.op != BRW_HIZ_OP_DEPTH_RESOLVE || ctx->Depth.Test);
+      assert(brw->hiz.op != BRW_HIZ_OP_HIZ_RESOLVE   || !ctx->Depth.Test);
+      assert(brw->hiz.op != BRW_HIZ_OP_DEPTH_CLEAR   || !ctx->Depth.Test);
+
+      ds->ds2.depth_test_enable = ctx->Depth.Test;
       ds->ds2.depth_test_func = intel_translate_compare_func(ctx->Depth.Func);
       ds->ds2.depth_write_enable = ctx->Depth.Mask;
    }
@@ -89,8 +98,9 @@ gen6_prepare_depth_stencil_state(struct brw_context *brw)
 const struct brw_tracked_state gen6_depth_stencil_state = {
    .dirty = {
       .mesa = _NEW_DEPTH | _NEW_STENCIL,
-      .brw = BRW_NEW_BATCH,
+      .brw  = (BRW_NEW_BATCH |
+              BRW_NEW_HIZ),
       .cache = 0,
    },
-   .prepare = gen6_prepare_depth_stencil_state,
+   .emit = gen6_upload_depth_stencil_state,
 };